12#include "common/phal_F4_F7/phal_F4_F7.h"
15 ADC_RES_12_BIT = 0b00,
16 ADC_RES_10_BIT = 0b01,
22 ADC_CLK_PRESC_2 = 0b00,
23 ADC_CLK_PRESC_4 = 0b01,
24 ADC_CLK_PRESC_6 = 0b10,
25 ADC_CLK_PRESC_8 = 0b11,
30 ADC_DMA_ONE_SHOT = 0b01,
31 ADC_DMA_CIRCULAR = 0b11
35 ADC_DATA_ALIGN_RIGHT = 0b0,
36 ADC_DATA_ALIGN_LEFT = 0b1
40 ADCClkPrescaler_t clock_prescaler;
41 ADCResolution_t resolution;
42 ADCDataAlign_t data_align;
44 ADCDMAMode_t dma_mode;
49 ADC_CHN_SMP_CYCLES_3 = 0b000,
50 ADC_CHN_SMP_CYCLES_15 = 0b001,
51 ADC_CHN_SMP_CYCLES_28 = 0b010,
52 ADC_CHN_SMP_CYCLES_56 = 0b011,
53 ADC_CHN_SMP_CYCLES_84 = 0b100,
54 ADC_CHN_SMP_CYCLES_112 = 0b101,
55 ADC_CHN_SMP_CYCLES_144 = 0b110,
56 ADC_CHN_SMP_CYCLES_480 = 0b111,
57} ADCChannelSampleCycles_t;
62 ADCChannelSampleCycles_t sampling_time;
66#define ADC1_DMA_CONT_CONFIG(mem_addr_, tx_size_, priority_) \
67 {.periph_addr = (uint32_t)&(ADC1->DR), .mem_addr = mem_addr_, .tx_size = tx_size_, .increment = true, .circular = true, .dir = 0b0, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, .priority = priority_, .mem_size = 0b01, .periph_size = 0b01, .tx_isr_en = false, .dma_chan_request = 0b0000, .stream_idx = 0, .periph = DMA2, .stream = DMA2_Stream0}
bool PHAL_startADC(ADC_TypeDef *adc)
Starts the ADC conversions, requires PHAL_initADC to be called prior.
Definition adc.c:82
uint16_t PHAL_readADC(ADC_TypeDef *adc)
Reads the ADC data register.
Definition adc.c:92
bool PHAL_stopADC(ADC_TypeDef *adc)
Stops the ADC conversions, requires PHAL_initADC to be called prior.
Definition adc.c:87
bool PHAL_initADC(ADC_TypeDef *adc, ADCInitConfig_t *config, ADCChannelConfig_t channels[], uint8_t num_channels)
Initializes the ADC, requires GPIO config prior.
Definition adc.c:11