rcc.h

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#ifndef _PHAL_RCC_H_
#define _PHAL_RCC_H_
 
#include "common/phal_F4_F7/phal_F4_F7.h"
 
#define HSE_CLOCK_RATE_HZ (16000000)
 
#define HSE_CLOCK_RATE_HZ_INVALID (1) /* High Speed External oscilator value */
#ifndef HSE_CLOCK_RATE_HZ
#define HSE_CLOCK_RATE_HZ HSE_CLOCK_RATE_HZ_INVALID /* Define this in order to configure clocks to use the HSE clock */
#endif // HSE_CLOCK_RATE_HZ
 
#define HSI_CLOCK_RATE_HZ (16000000)
#define MCO_OUT_PIN       (8)
 
// RCC Constants
#if defined(STM32F407xx)
 
#define RCC_MAX_VCO_RATE_HZ           ((uint32_t)432e6)
#define RCC_MIN_VCO_RATE_HZ           ((uint32_t)100e6)
#define RCC_MIN_PLL_INPUT_DIVISOR     (2U)
#define RCC_MAX_PLL_INPUT_DIVISOR     (63U)
#define RCC_MIN_PLL_OUTPUT_MULTIPLIER (50U)
#define RCC_MAX_PLL_OUTPUT_MULTIPLIER (432U)
#define RCC_MAX_SYSCLK_TARGET_HZ      (168000000)
 
#elif defined(STM32F732xx)
 
#define RCC_MAX_VCO_RATE_HZ           ((uint32_t)432e6)
#define RCC_MIN_VCO_RATE_HZ           ((uint32_t)100e6)
#define RCC_MIN_PLL_INPUT_DIVISOR     (2U)
#define RCC_MAX_PLL_INPUT_DIVISOR     (63U)
#define RCC_MIN_PLL_OUTPUT_MULTIPLIER (50U)
#define RCC_MAX_PLL_OUTPUT_MULTIPLIER (432U)
#define RCC_MAX_SYSCLK_TARGET_HZ      (216000000)
 
#else
#error "Please define a MCU arch"
#endif
 
typedef enum {
    PLL_SRC_HSI16,
    PLL_SRC_HSE
} PLLSrc_t;
 
typedef enum {
    MCO1_SRC_HSI = 0,
    MCO1_SRC_LSE = 1,
    MCO1_SRC_HSE = 2,
    MCO1_SRC_PLL = 3,
 
} MCO1Source_t;
 
typedef enum {
    MCO_DIV_NONE = 0,
    MCO_DIV_2    = 4,
    MCO_DIV_3    = 5,
    MCO_DIV_4    = 6,
    MCO_DIV_5    = 7
 
} MCODivisor_t;
 
typedef enum {
    CLOCK_SOURCE_HSI = 0,
    CLOCK_SOURCE_HSE = 1,
} ClockSrc_t;
 
typedef enum {
    RCC_ERROR_AHB_INIT    = 0,
    RCC_ERROR_APB1_INIT   = 1,
    RCC_ERROR_APB2_INIT   = 2,
    RCC_ERROR_HSI_INIT    = 3,
    RCC_ERROR_PLLSYS_INIT = 4,
    RCC_ERROR_PLLVCO_INIT = 5,
    RCC_ERROR_HSE_INIT    = 6,
} RCCErrors_t;
 
typedef struct {
    ClockSrc_t clock_source; /* Use HSE or not */
    bool use_pll; /* Use PLL or not */
    uint32_t system_clock_target_hz; /* System Core Clock rate */
    uint32_t ahb_clock_target_hz; /* AHB clock rate target */
    uint32_t apb1_clock_target_hz; /* APB1 clock rate target */
    uint32_t apb2_clock_target_hz; /* APB2 clock rate target */
 
    /* Only used for use_pll == true */
    PLLSrc_t pll_src; /* Input source for PLL VCO */
    uint32_t vco_output_rate_target_hz; /* VCO output target rate */
    uint32_t msi_output_rate_target_hz; /* Use if pll_src == MSI */
} ClockRateConfig_t;
 
uint8_t PHAL_configureClockRates(ClockRateConfig_t* config);
 
bool PHAL_configurePLLVCO(PLLSrc_t pll_source, uint32_t vco_output_rate_target_hz);
 
bool PHAL_configurePLLSystemClock(uint32_t system_clock_target_hz);
 
bool PHAL_configureHSISystemClock();
 
bool PHAL_configureHSESystemClock();
 
bool PHAL_configureAHBClock(uint32_t ahb_clock_target_hz);
 
bool PHAL_configureAPB1Clock(uint32_t apb1_clock_target_hz);
 
bool PHAL_configureAPB2Clock(uint32_t apb2_clock_target_hz);
 
void PHAL_trimHSI(uint8_t trim_val);
 
bool PHAL_enableMCO1(GPIO_TypeDef* bank, uint8_t pin, MCO1Source_t source, MCODivisor_t division);
 
#endif // _PHAL_PLL_H_