usart.h

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#ifndef _PHAL_USART_H_
#define _PHAL_USART_H_
 
// Includes
#if defined(STM32F407xx)
#define TOTAL_NUM_UART 8
 
// Active Transfer list indexes (Add to this list if updating TOTAL_NUM_UART)
#define USART1_ACTIVE_IDX 0
#define USART2_ACTIVE_IDX 1
#define USART3_ACTIVE_IDX 2
#define USART4_ACTIVE_IDX 3
#define USART5_ACTIVE_IDX 4
#define USART6_ACTIVE_IDX 5
#define USART7_ACTIVE_IDX 6
#define USART8_ACTIVE_IDX 7
 
#elif defined(STM32F732xx)
#define TOTAL_NUM_UART             8
 
// Active Transfer list indexes (Add to this list if updating TOTAL_NUM_UART)
#define USART1_ACTIVE_IDX          0
#define USART2_ACTIVE_IDX          1
#define USART3_ACTIVE_IDX          2
#define USART4_ACTIVE_IDX          3
#define USART5_ACTIVE_IDX          4
#define USART6_ACTIVE_IDX          5
#define USART7_ACTIVE_IDX          6
#define USART8_ACTIVE_IDX          7
 
// Defines that mean the same thing but are phrased differently in stm32f4xx and stm32f7xx
#define USART_BRR_DIV_Fraction_Pos USART_BRR_DIV_FRACTION_Pos
#define USART_BRR_DIV_Mantissa_Pos USART_BRR_DIV_MANTISSA_Pos
#endif
 
#include "common/phal_F4_F7/dma/dma.h"
#include "common/phal_F4_F7/phal_F4_F7.h"
 
typedef uint32_t ptr_int;
 
// See USART section of Family reference manual (RM0090 for F4, or RM0431 for F7) for configuration information
 
// Enumerations
// See Table 146 in RM. 0090
// By enabling Parity, you sacrifice one bit from your total word length
// (eg. if WORD_8 is selected, you now have 7 data bits and 1 parity bit)
typedef enum {
    PT_EVEN = 0b010, 
    PT_ODD  = 0b100, 
    PT_NONE = 0b000 
} parity_t;
 
typedef enum {
    WORD_8, 
    WORD_9, 
} word_length_t;
 
typedef enum {
    SB_ONE      = 0b00, 
    SB_TWO      = 0b01, 
    SB_HALF     = 0b10, 
    SB_ONE_HALF = 0b11 
} stop_bits_t;
 
typedef enum {
    HW_DISABLE, 
    CTS, 
    RTS, 
    CTS_RTS 
} hw_flow_ctl_t;
 
typedef enum {
    OV_16 = 0, 
    OV_8  = 1 
} ovsample_t;
 
typedef enum {
    OB_DISABLE, 
    OB_ENABLE 
} obsample_t;
 
typedef struct
{
    bool overrun; 
    bool noise_detected; 
    bool framing_error; 
    bool parity_error; 
 
    // DMA Errors
    bool dma_transfer_error; 
    bool dma_direct_mode_error; 
    bool dma_fifo_overrun; 
} usart_rx_errors_t;
 
typedef struct
{
    bool dma_transfer_error; 
    bool dma_direct_mode_error; 
    bool dma_fifo_overrun; 
} usart_tx_errors_t;
 
// Structures
typedef struct
{
    // Required parameters
    uint32_t baud_rate; 
    word_length_t word_length; 
    stop_bits_t stop_bits; 
    parity_t parity; 
    hw_flow_ctl_t hw_flow_ctl; 
    ovsample_t ovsample; 
    obsample_t obsample; 
    bool wake_addr; 
    uint8_t address; 
    uint8_t usart_active_num; 
 
    // DMA configurations
    dma_init_t* tx_dma_cfg; 
    dma_init_t* rx_dma_cfg; 
    USART_TypeDef* periph; 
 
    // Structs to communicate errors to user
    volatile usart_tx_errors_t tx_errors; 
    volatile usart_rx_errors_t rx_errors; 
} usart_init_t;
 
// Function Prototypes
 
bool PHAL_initUSART(usart_init_t* handle, const uint32_t fck);
 
void PHAL_usartTxBl(usart_init_t* handle, uint8_t* data, uint32_t len);
 
void PHAL_usartRxBl(usart_init_t* handle, uint8_t* data, uint32_t len);
 
bool PHAL_usartTxDma(usart_init_t* handle, uint16_t* data, uint32_t len);
 
bool PHAL_usartRxDma(usart_init_t* handle, uint16_t* data, uint32_t len, bool cont);
 
bool PHAL_disableContinousRxDMA(usart_init_t* handle);
 
bool PHAL_usartTxBusy(usart_init_t* handle);
 
bool PHAL_usartRxBusy(usart_init_t* handle);
 
extern void usart_recieve_complete_callback(usart_init_t* handle);
 
#ifdef STM32F407xx
// 4,5,7,8 are UART, rest are USART
#define PHAL_USART1_RXDMA_STREAM DMA2_Stream5
#define PHAL_USART1_TXDMA_STREAM DMA2_Stream7
 
#define PHAL_USART2_RXDMA_STREAM DMA1_Stream5
#define PHAL_USART2_TXDMA_STREAM DMA1_Stream6
 
#define PHAL_USART3_RXDMA_STREAM DMA1_Stream1
#define PHAL_USART3_TXDMA_STREAM DMA1_Stream3
 
#define PHAL_USART4_RXDMA_STREAM DMA1_Stream2 // UART
#define PHAL_USART4_TXDMA_STREAM DMA1_Stream4
 
#define PHAL_USART5_RXDMA_STREAM DMA1_Stream0 // UART
#define PHAL_USART5_TXDMA_STREAM DMA1_Stream7
 
#define PHAL_USART6_RXDMA_STREAM DMA2_Stream1
#define PHAL_USART6_TXDMA_STREAM DMA2_Stream6
 
#define PHAL_USART7_RXDMA_STREAM DMA1_Stream3 // UART
#define PHAL_USART7_TXDMA_STREAM DMA1_Stream1
 
#define PHAL_USART8_RXDMA_STREAM DMA1_Stream6 // UART
#define PHAL_USART8_TXDMA_STREAM DMA1_Stream0
// dm00031020 311
#define _DEF_USART_RXDMA_CONFIG(rx_addr_, priority_, UXART, dmanum, streamnum, channum) \
    { \
        .periph_addr      = (uint32_t)&((UXART)->DR), \
        .mem_addr         = (uint32_t)(rx_addr_), \
        .tx_size          = 1, \
        .increment        = false, \
        .circular         = false, \
        .dir              = 0b0, \
        .mem_inc          = true, \
        .periph_inc       = false, \
        .mem_to_mem       = false, \
        .priority         = (priority_), \
        .mem_size         = 0b00, \
        .periph_size      = 0b00, \
        .tx_isr_en        = true, \
        .dma_chan_request = channum, \
        .stream_idx       = streamnum, \
        .periph           = DMA##dmanum, \
        .stream           = DMA##dmanum##_Stream##streamnum, \
    }
 
#define _DEF_USART_TXDMA_CONFIG(tx_addr_, priority_, UXART, dmanum, streamnum, channum) \
    { \
        .periph_addr      = (uint32_t)&((UXART)->DR), \
        .mem_addr         = (uint32_t)(tx_addr_), \
        .tx_size          = 1, \
        .increment        = false, \
        .circular         = false, \
        .dir              = 0b1, \
        .mem_inc          = true, \
        .periph_inc       = false, \
        .mem_to_mem       = false, \
        .priority         = (priority_), \
        .mem_size         = 0b00, \
        .periph_size      = 0b00, \
        .tx_isr_en        = true, \
        .dma_chan_request = channum, \
        .stream_idx       = streamnum, \
        .periph           = DMA##dmanum, \
        .stream           = DMA##dmanum##_Stream##streamnum, \
    }
 
#define USART1_RXDMA_CONT_CONFIG(a, p) _DEF_USART_RXDMA_CONFIG(a, p, USART1, 2, 5, 4)
#define USART1_TXDMA_CONT_CONFIG(a, p) _DEF_USART_TXDMA_CONFIG(a, p, USART1, 2, 7, 4)
#define USART2_RXDMA_CONT_CONFIG(a, p) _DEF_USART_RXDMA_CONFIG(a, p, USART2, 1, 5, 4)
#define USART2_TXDMA_CONT_CONFIG(a, p) _DEF_USART_TXDMA_CONFIG(a, p, USART2, 1, 6, 4)
#define USART3_RXDMA_CONT_CONFIG(a, p) _DEF_USART_RXDMA_CONFIG(a, p, USART3, 1, 1, 4)
#define USART3_TXDMA_CONT_CONFIG(a, p) _DEF_USART_TXDMA_CONFIG(a, p, USART3, 1, 3, 4)
#define USART4_RXDMA_CONT_CONFIG(a, p) _DEF_USART_RXDMA_CONFIG(a, p, UART4, 1, 2, 4)
#define USART4_TXDMA_CONT_CONFIG(a, p) _DEF_USART_TXDMA_CONFIG(a, p, UART4, 1, 4, 4)
#define USART5_RXDMA_CONT_CONFIG(a, p) _DEF_USART_RXDMA_CONFIG(a, p, UART5, 1, 0, 4)
#define USART5_TXDMA_CONT_CONFIG(a, p) _DEF_USART_TXDMA_CONFIG(a, p, UART5, 1, 7, 4)
#define USART6_RXDMA_CONT_CONFIG(a, p) _DEF_USART_RXDMA_CONFIG(a, p, USART6, 2, 1, 5)
#define USART6_TXDMA_CONT_CONFIG(a, p) _DEF_USART_TXDMA_CONFIG(a, p, USART6, 2, 6, 5)
 
#else
 
#define USART1_RXDMA_CONT_CONFIG(rx_addr_, priority_) \
    { \
        .periph_addr      = (uint32_t)&(USART1->RDR), \
        .mem_addr         = (uint32_t)(rx_addr_), \
        .tx_size          = 1, \
        .increment        = false, \
        .circular         = false, \
        .dir              = 0b0, \
        .mem_inc          = true, \
        .periph_inc       = false, \
        .mem_to_mem       = false, \
        .priority         = (priority_), \
        .mem_size         = 0b00, \
        .periph_size      = 0b00, \
        .tx_isr_en        = true, \
        .dma_chan_request = 0b0100, \
        .stream_idx       = 5, \
        .periph           = DMA2, \
        .stream           = DMA2_Stream5}
 
#define USART1_TXDMA_CONT_CONFIG(tx_addr_, priority_) \
    { \
        .periph_addr      = (uint32_t)&(USART1->TDR), \
        .mem_addr         = (uint32_t)(tx_addr_), \
        .tx_size          = 1, \
        .increment        = false, \
        .circular         = false, \
        .dir              = 0b1, \
        .mem_inc          = true, \
        .periph_inc       = false, \
        .mem_to_mem       = false, \
        .priority         = (priority_), \
        .mem_size         = 0b00, \
        .periph_size      = 0b00, \
        .tx_isr_en        = true, \
        .dma_chan_request = 0b0100, \
        .stream_idx       = 7, \
        .periph           = DMA2, \
        .stream           = DMA2_Stream7}
 
#define USART4_RXDMA_CONT_CONFIG(rx_addr_, priority_) \
    { \
        .periph_addr      = (uint32_t)&(UART4->RDR), \
        .mem_addr         = (uint32_t)(rx_addr_), \
        .tx_size          = 1, \
        .increment        = false, \
        .circular         = false, \
        .dir              = 0b0, \
        .mem_inc          = true, \
        .periph_inc       = false, \
        .mem_to_mem       = false, \
        .priority         = (priority_), \
        .mem_size         = 0b00, \
        .periph_size      = 0b00, \
        .tx_isr_en        = true, \
        .dma_chan_request = 0b0100, \
        .stream_idx       = 2, \
        .periph           = DMA1, \
        .stream           = DMA1_Stream2}
 
#define USART4_TXDMA_CONT_CONFIG(tx_addr_, priority_) \
    { \
        .periph_addr      = (uint32_t)&(UART4->TDR), \
        .mem_addr         = (uint32_t)(tx_addr_), \
        .tx_size          = 1, \
        .increment        = false, \
        .circular         = false, \
        .dir              = 0b1, \
        .mem_inc          = true, \
        .periph_inc       = false, \
        .mem_to_mem       = false, \
        .priority         = (priority_), \
        .mem_size         = 0b00, \
        .periph_size      = 0b00, \
        .tx_isr_en        = true, \
        .dma_chan_request = 0b0100, \
        .stream_idx       = 4, \
        .periph           = DMA1, \
        .stream           = DMA1_Stream4}
 
#define UART5_RXDMA_CONT_CONFIG(rx_addr_, priority_) \
    { \
        .periph_addr      = (uint32_t)&(UART5->RDR), \
        .mem_addr         = (uint32_t)(rx_addr_), \
        .tx_size          = 1, \
        .increment        = false, \
        .circular         = false, \
        .dir              = 0b0, \
        .mem_inc          = true, \
        .periph_inc       = false, \
        .mem_to_mem       = false, \
        .priority         = (priority_), \
        .mem_size         = 0b00, \
        .periph_size      = 0b00, \
        .tx_isr_en        = true, \
        .dma_chan_request = 0b0100, \
        .stream_idx       = 0, \
        .periph           = DMA1, \
        .stream           = DMA1_Stream0}
#define UART5_TXDMA_CONT_CONFIG(tx_addr_, priority_) \
    { \
        .periph_addr      = (uint32_t)&(UART5->TDR), \
        .mem_addr         = (uint32_t)(tx_addr_), \
        .tx_size          = 1, \
        .increment        = false, \
        .circular         = false, \
        .dir              = 0b1, \
        .mem_inc          = true, \
        .periph_inc       = false, \
        .mem_to_mem       = false, \
        .priority         = (priority_), \
        .mem_size         = 0b00, \
        .periph_size      = 0b00, \
        .tx_isr_en        = true, \
        .dma_chan_request = 0b0100, \
        .stream_idx       = 7, \
        .periph           = DMA1, \
        .stream           = DMA1_Stream7}
#endif
#endif