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dma.h
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1
12#ifndef __PHAL_G4_DMA_H__
13#define __PHAL_G4_DMA_H__
14
15#include "common/phal_G4/phal_G4.h"
16
17typedef enum {
18 DMA_SIZE_8BIT = 0,
19 DMA_SIZE_16BIT = 1,
20 DMA_SIZE_32BIT = 2
21} dma_size_t;
22
23// Mux requests (TODO support all)
24#define DMA_REQUEST_ADC1 5U
25#define DMA_REQUEST_ADC2 36U
26#define DMA_REQUEST_ADC3 37U
27#define DMA_REQUEST_ADC4 38U
28
29#define DMA_REQUEST_SPI1_RX 10U
30#define DMA_REQUEST_SPI1_TX 11U
31#define DMA_REQUEST_SPI2_RX 12U
32#define DMA_REQUEST_SPI2_TX 13U
33#define DMA_REQUEST_SPI3_RX 14U
34#define DMA_REQUEST_SPI3_TX 15U
35
36#define DMA_REQUEST_USART1_RX 24U
37#define DMA_REQUEST_USART1_TX 25U
38#define DMA_REQUEST_USART2_RX 26U
39#define DMA_REQUEST_USART2_TX 27U
40#define DMA_REQUEST_USART3_RX 28U
41#define DMA_REQUEST_USART3_TX 29U
42
43typedef struct {
44 uint32_t periph_addr;
45 uint32_t mem_addr;
46 uint16_t tx_size;
47 uint8_t mem_size;
48
49 bool increment;
50 bool circular;
51 uint8_t dir;
52 bool mem_inc;
53 bool periph_inc;
54 bool mem_to_mem;
55 uint8_t priority;
56 uint8_t periph_size;
57 bool tx_isr_en;
58 uint8_t dma_chan_request;
59 uint8_t channel_idx;
60 uint8_t mux_request;
61
62 DMA_TypeDef* periph;
63 DMA_Channel_TypeDef* channel; // Example DMA1_Stream0 or DMA2_Stream7
65
66/*
67 * @brief Initialize DMA peripheral to set m2m, p2p, or p2m with set size
68 * and length of txfer
69 *
70 * @param dma -> Address of initialization structure
71 * @return true -> Successful init (no clashing params)
72 * @return false -> Init not complete (parameters clash)
73 */
74bool PHAL_initDMA(dma_init_t* dma);
75
76/*
77 * @brief Start txfer after sucessful DMA peripheral initialization
78 *
79 * @param dma -> Address of initialization structure
80 */
81void PHAL_startTxfer(dma_init_t* dma);
82
83/*
84 * @brief Stop txfer
85 *
86 * @param dma -> Address of initialization structure
87 */
88void PHAL_stopTxfer(dma_init_t* dma);
89
90/*
91 * @brief Re-enable DMA txfer after error ISR fires
92 *
93 * @param dma -> Address of initialization structure
94 */
95void PHAL_reEnable(dma_init_t* dma);
96
97/*
98 * @brief Set memory address for DMA transfer. In Mem to Mem this acts as the source address
99 *
100 * @param dma -> Address of initialization structure
101 */
102void PHAL_DMA_setMemAddress(dma_init_t* dma, const uint32_t address);
103
104/*
105 * @brief Set transfer length for DMA transaction
106 *
107 * @param dma -> Address of initialization structure
108 */
109void PHAL_DMA_setTxferLength(dma_init_t* dma, const uint32_t length);
110
111#endif // __PHAL_G4_DMA_H__
Definition dma.h:17