usart.h

#ifndef _PHAL_USART_H_
#define _PHAL_USART_H_
 
// Includes
#define TOTAL_NUM_UART 8
 
// Active Transfer list indexes (Add to this list if updating TOTAL_NUM_UART)
#define USART1_ACTIVE_IDX  0
#define USART2_ACTIVE_IDX  1
#define USART3_ACTIVE_IDX  2
#define UART4_ACTIVE_IDX   3
#define LPUART1_ACTIVE_IDX 4
#define USART5_ACTIVE_IDX  5
#define USART6_ACTIVE_IDX  6
#define USART7_ACTIVE_IDX  7
 
#include "common/phal_G4/dma/dma.h"
#include "common/phal_G4/phal_G4.h"
 
typedef uint32_t ptr_int;
 
// Enumerations
// See USART section of Family reference manual for configuration information
 
typedef enum {
    PT_EVEN = 0b010, 
    PT_ODD  = 0b100, 
    PT_NONE = 0b000 
} parity_t;
 
typedef enum {
    WORD_7,
    WORD_8, 
    WORD_9, 
} word_length_t;
 
typedef enum {
    SB_ONE      = 0b00, 
    SB_TWO      = 0b01, 
    SB_HALF     = 0b10, 
    SB_ONE_HALF = 0b11 
} stop_bits_t;
 
typedef enum {
    HW_DISABLE, 
    CTS, 
    RTS, 
    CTS_RTS 
} hw_flow_ctl_t;
 
typedef enum {
    OV_16 = 0, 
    OV_8  = 1 
} ovsample_t;
 
typedef enum {
    OB_DISABLE, 
    OB_ENABLE 
} obsample_t;
 
typedef struct {
    bool overrun; 
    bool noise_detected; 
    bool framing_error; 
    bool parity_error; 
 
    // DMA Errors
    bool dma_transfer_error; 
    bool dma_direct_mode_error; 
    bool dma_fifo_overrun; 
} usart_rx_errors_t;
 
typedef struct {
    bool dma_transfer_error; 
    bool dma_direct_mode_error; 
    bool dma_fifo_overrun; 
} usart_tx_errors_t;
 
// Structures
typedef struct {
    // Required parameters
    uint32_t baud_rate; 
    word_length_t word_length; 
    stop_bits_t stop_bits; 
    parity_t parity; 
    hw_flow_ctl_t hw_flow_ctl; 
    ovsample_t ovsample; 
    obsample_t obsample; 
    bool wake_addr; 
    uint8_t address; 
    uint8_t usart_active_num; 
 
    // DMA configurations
    dma_init_t* tx_dma_cfg; 
    dma_init_t* rx_dma_cfg; 
    USART_TypeDef* periph; 
 
    // Structs to communicate errors to user
    volatile usart_tx_errors_t tx_errors; 
    volatile usart_rx_errors_t rx_errors; 
} usart_init_t;
 
// Function Prototypes
 
bool PHAL_initUSART(usart_init_t* handle, const uint32_t fck);
 
void PHAL_usartTxBl(usart_init_t* handle, uint8_t* data, uint32_t len);
 
void PHAL_usartRxBl(usart_init_t* handle, uint8_t* data, uint32_t len);
 
bool PHAL_usartTxDma(usart_init_t* handle, uint8_t* data, uint32_t len);
 
bool PHAL_usartRxDma(usart_init_t* handle, uint8_t* data, uint32_t len, bool cont);
 
bool PHAL_disableContinousRxDMA(usart_init_t* handle);
 
volatile bool PHAL_usartTxBusy(usart_init_t* handle);
 
bool PHAL_usartRxBusy(usart_init_t* handle);
 
extern void usart_receive_complete_callback(usart_init_t* handle);
 
 
#define _DEF_USART_RXDMA_CONFIG(rx_addr_, priority_, USARTx, dma_num, channel_num, req_id) \
    { \
        .periph_addr = (uint32_t)&((USARTx)->RDR), \
        .mem_addr    = (uint32_t)(rx_addr_), \
        .tx_size     = 1, \
        .circular    = false, \
        .mem_inc     = true, \
        .periph_inc  = false, \
        .mem_to_mem  = false, \
        .priority    = (priority_), \
        .dir         = 0, \
        .mem_size    = DMA_SIZE_8BIT, \
        .periph_size = DMA_SIZE_8BIT, \
        .tx_isr_en   = true, \
        .mux_request = (req_id), \
        .channel_idx = (channel_num), \
        .periph      = DMA##dma_num, \
    }
 
#define _DEF_USART_TXDMA_CONFIG(tx_addr_, priority_, USARTx, dma_num, channel_num, req_id) \
    { \
        .periph_addr = (uint32_t)&((USARTx)->TDR), \
        .mem_addr    = (uint32_t)(tx_addr_), \
        .tx_size     = 1, \
        .circular    = false, \
        .mem_inc     = true, \
        .periph_inc  = false, \
        .mem_to_mem  = false, \
        .priority    = (priority_), \
        .dir         = 1, \
        .mem_size    = DMA_SIZE_8BIT, \
        .periph_size = DMA_SIZE_8BIT, \
        .tx_isr_en   = true, \
        .mux_request = (req_id), \
        .channel_idx = (channel_num), \
        .periph      = DMA##dma_num, \
    }
 
#define USART1_RXDMA_CONT_CONFIG(a, p) \
    _DEF_USART_RXDMA_CONFIG(a, p, USART1, 1, 5, DMA_REQUEST_USART1_RX)
#define USART1_TXDMA_CONT_CONFIG(a, p) \
    _DEF_USART_TXDMA_CONFIG(a, p, USART1, 1, 7, DMA_REQUEST_USART1_TX)
 
#define USART2_RXDMA_CONT_CONFIG(a, p) \
    _DEF_USART_RXDMA_CONFIG(a, p, USART2, 1, 3, DMA_REQUEST_USART2_RX)
#define USART2_TXDMA_CONT_CONFIG(a, p) \
    _DEF_USART_TXDMA_CONFIG(a, p, USART2, 1, 4, DMA_REQUEST_USART2_TX)
 
#define USART3_RXDMA_CONT_CONFIG(a, p) \
    _DEF_USART_RXDMA_CONFIG(a, p, USART3, 1, 1, DMA_REQUEST_USART3_RX)
#define USART3_TXDMA_CONT_CONFIG(a, p) \
    _DEF_USART_TXDMA_CONFIG(a, p, USART3, 1, 2, DMA_REQUEST_USART3_TX)
 
#define UART4_RXDMA_CONT_CONFIG(a, p) \
    _DEF_USART_RXDMA_CONFIG(a, p, UART4, 2, 5, DMA_REQUEST_UART4_RX)
#define UART4_TXDMA_CONT_CONFIG(a, p) \
    _DEF_USART_TXDMA_CONFIG(a, p, UART4, 2, 3, DMA_REQUEST_UART4_TX)
 
#define LPUART1_RXDMA_CONT_CONFIG(a, p) \
    _DEF_USART_RXDMA_CONFIG(a, p, LPUART1, 2, 6, DMA_REQUEST_LPUART1_RX)
#define LPUART1_TXDMA_CONT_CONFIG(a, p) \
    _DEF_USART_TXDMA_CONFIG(a, p, LPUART1, 2, 7, DMA_REQUEST_LPUART1_TX)
 
#endif