Common register group
It set the basic for the networking
It set the configuration such as interrupt, network information, ICMP, etc. More...

Macros
#define	MR (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_CREG_BLOCK << 3))
	Mode Register address(R/W) MR is used for S/W reset, ping block mode, PPPoE mode and etc.

#define	GAR (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_CREG_BLOCK << 3))
	Gateway IP Register address(R/W)

#define	SUBR (_W5500_IO_BASE_ + (0x0005 << 8) + (WIZCHIP_CREG_BLOCK << 3))
	Subnet mask Register address(R/W)

#define	SHAR (_W5500_IO_BASE_ + (0x0009 << 8) + (WIZCHIP_CREG_BLOCK << 3))
	Source MAC Register address(R/W)

#define	SIPR (_W5500_IO_BASE_ + (0x000F << 8) + (WIZCHIP_CREG_BLOCK << 3))
	Source IP Register address(R/W)

#define	INTLEVEL (_W5500_IO_BASE_ + (0x0013 << 8) + (WIZCHIP_CREG_BLOCK << 3))
	Set Interrupt low level timer register address(R/W)

#define	IR (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_CREG_BLOCK << 3))
	Interrupt Register(R/W)

#define	_IMR_ (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_CREG_BLOCK << 3))
	Interrupt mask register(R/W)

#define	SIR (_W5500_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_CREG_BLOCK << 3))
	Socket Interrupt Register(R/W)

#define	SIMR (_W5500_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_CREG_BLOCK << 3))
	Socket Interrupt Mask Register(R/W)

#define	_RTR_ (_W5500_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_CREG_BLOCK << 3))
	Timeout register address( 1 is 100us )(R/W)

#define	_RCR_ (_W5500_IO_BASE_ + (0x001B << 8) + (WIZCHIP_CREG_BLOCK << 3))
	Retry count register(R/W)

#define	PTIMER (_W5500_IO_BASE_ + (0x001C << 8) + (WIZCHIP_CREG_BLOCK << 3))
	PPP LCP Request Timer register in PPPoE mode(R/W)

#define	PMAGIC (_W5500_IO_BASE_ + (0x001D << 8) + (WIZCHIP_CREG_BLOCK << 3))
	PPP LCP Magic number register in PPPoE mode(R/W)

#define	PHAR (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_CREG_BLOCK << 3))
	PPP Destination MAC Register address(R/W)

#define	PSID (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_CREG_BLOCK << 3))
	PPP Session Identification Register(R/W)

#define	PMRU (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_CREG_BLOCK << 3))
	PPP Maximum Segment Size(MSS) register(R/W)

#define	UIPR (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_CREG_BLOCK << 3))
	Unreachable IP register address in UDP mode(R)

#define	UPORTR (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_CREG_BLOCK << 3))
	Unreachable Port register address in UDP mode(R)

#define	PHYCFGR (_W5500_IO_BASE_ + (0x002E << 8) + (WIZCHIP_CREG_BLOCK << 3))
	PHY Status Register(R/W)

#define	VERSIONR (_W5500_IO_BASE_ + (0x0039 << 8) + (WIZCHIP_CREG_BLOCK << 3))
	chip version register address(R)

Detailed Description

Common register group
It set the basic for the networking
It set the configuration such as interrupt, network information, ICMP, etc.

See also: MR : Mode register.; GAR, SUBR, SHAR, SIPR; INTLEVEL, IR, IMR, SIR, SIMR : Interrupt.; RTR, RCR : Data retransmission.; PTIMER, PMAGIC, PHAR, PSID, PMRU : PPPoE.; UIPR, UPORTR : ICMP message.; PHYCFGR, VERSIONR : etc.

Macro Definition Documentation

◆ _IMR_

#define _IMR_ (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Interrupt mask register(R/W)

_IMR_ is used to mask interrupts. Each bit of _IMR_ corresponds to each bit of IR. When a bit of _IMR_ is and the corresponding bit of IR is an interrupt will be issued. In other words, if a bit of _IMR_ is an interrupt will not be issued even if the corresponding bit of IR is

Each bit of _IMR_ defined as the following.

7	6	5	4	3	2	1	0
IM_IR7	IM_IR6	IM_IR5	IM_IR4	Reserved	Reserved	Reserved	Reserved

IM_IR7 : IP Conflict Interrupt Mask
IM_IR6 : Destination unreachable Interrupt Mask
IM_IR5 : PPPoE Close Interrupt Mask
IM_IR4 : Magic Packet Interrupt Mask

◆ _RCR_

#define _RCR_ (_W5500_IO_BASE_ + (0x001B << 8) + (WIZCHIP_CREG_BLOCK << 3))

Retry count register(R/W)

_RCR_ configures the number of time of retransmission. When retransmission occurs as many as ref RCR+1 Timeout interrupt is issued (Sn_IR_TIMEOUT = '1').

◆ _RTR_

#define _RTR_ (_W5500_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Timeout register address( 1 is 100us )(R/W)

_RTR_ configures the retransmission timeout period. The unit of timeout period is 100us and the default of _RTR_ is x07D0. And so the default timeout period is 200ms(100us X 2000). During the time configured by _RTR_, W5500 waits for the peer response to the packet that is transmitted by Sn_CR (CONNECT, DISCON, CLOSE, SEND, SEND_MAC, SEND_KEEP command). If the peer does not respond within the _RTR_ time, W5500 retransmits the packet or issues timeout.

◆ GAR

#define GAR (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Gateway IP Register address(R/W)

GAR configures the default gateway address.

◆ INTLEVEL

#define INTLEVEL (_W5500_IO_BASE_ + (0x0013 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Set Interrupt low level timer register address(R/W)

INTLEVEL configures the Interrupt Assert Time.

◆ IR

#define IR (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Interrupt Register(R/W)

IR indicates the interrupt status. Each bit of IR will be still until the bit will be written to by the host. If IR is not equal to x00 INTn PIN is asserted to low until it is x00

Each bit of IR defined as follows.

7	6	5	4	3	2	1	0
CONFLICT	UNREACH	PPPoE	MP	Reserved	Reserved	Reserved	Reserved

IR_CONFLICT : IP conflict
IR_UNREACH : Destination unreachable
IR_PPPoE : PPPoE connection close
IR_MP : Magic packet

◆ MR

#define MR (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Mode Register address(R/W)
MR is used for S/W reset, ping block mode, PPPoE mode and etc.

Each bit of MR defined as follows.

7	6	5	4	3	2	1	0
RST	Reserved	WOL	PB	PPPoE	Reserved	FARP	Reserved

MR_RST : Reset
MR_WOL : Wake on LAN
MR_PB : Ping block
MR_PPPOE : PPPoE mode
MR_FARP : Force ARP mode

◆ PHAR

#define PHAR (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_CREG_BLOCK << 3))

PPP Destination MAC Register address(R/W)

PHAR configures the PPPoE server hardware address that is acquired during PPPoE connection process.

◆ PHYCFGR

#define PHYCFGR (_W5500_IO_BASE_ + (0x002E << 8) + (WIZCHIP_CREG_BLOCK << 3))

PHY Status Register(R/W)

PHYCFGR configures PHY operation mode and resets PHY. In addition, PHYCFGR indicates the status of PHY such as duplex, Speed, Link.

◆ PMAGIC

#define PMAGIC (_W5500_IO_BASE_ + (0x001D << 8) + (WIZCHIP_CREG_BLOCK << 3))

PPP LCP Magic number register in PPPoE mode(R/W)

PMAGIC configures the 4bytes magic number to be used in LCP negotiation.

◆ PMRU

#define PMRU (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_CREG_BLOCK << 3))

PPP Maximum Segment Size(MSS) register(R/W)

PMRU configures the maximum receive unit of PPPoE.

◆ PSID

#define PSID (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_CREG_BLOCK << 3))

PPP Session Identification Register(R/W)

PSID configures the PPPoE sever session ID acquired during PPPoE connection process.

◆ PTIMER

#define PTIMER (_W5500_IO_BASE_ + (0x001C << 8) + (WIZCHIP_CREG_BLOCK << 3))

PPP LCP Request Timer register in PPPoE mode(R/W)

PTIMER configures the time for sending LCP echo request. The unit of time is 25ms.

◆ SHAR

#define SHAR (_W5500_IO_BASE_ + (0x0009 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Source MAC Register address(R/W)

SHAR configures the source hardware address.

◆ SIMR

#define SIMR (_W5500_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Socket Interrupt Mask Register(R/W)

Each bit of SIMR corresponds to each bit of SIR. When a bit of SIMR is and the corresponding bit of SIR is Interrupt will be issued. In other words, if a bit of SIMR is an interrupt will be not issued even if the corresponding bit of SIR is

◆ SIPR

#define SIPR (_W5500_IO_BASE_ + (0x000F << 8) + (WIZCHIP_CREG_BLOCK << 3))

Source IP Register address(R/W)

SIPR configures the source IP address.

◆ SIR

#define SIR (_W5500_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Socket Interrupt Register(R/W)

SIR indicates the interrupt status of Socket.
Each bit of SIR be still until Sn_IR is cleared by the host.
If Sn_IR is not equal to x00 the n-th bit of SIR is and INTn PIN is asserted until SIR is x00

◆ SUBR

#define SUBR (_W5500_IO_BASE_ + (0x0005 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Subnet mask Register address(R/W)

SUBR configures the subnet mask address.

◆ UIPR

#define UIPR (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Unreachable IP register address in UDP mode(R)

W5500 receives an ICMP packet(Destination port unreachable) when data is sent to a port number which socket is not open and IR_UNREACH bit of IR becomes and UIPR & UPORTR indicates the destination IP address & port number respectively.

◆ UPORTR

#define UPORTR (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_CREG_BLOCK << 3))

Unreachable Port register address in UDP mode(R)