W5500 HAL Header File. More...

#include <stdint.h>
#include "wizchip_conf.h"

Macros
#define	_W5500_IO_BASE_ 0x00000000

#define	_W5500_SPI_READ_ (0x00 << 2)

#define	_W5500_SPI_WRITE_ (0x01 << 2)

#define	WIZCHIP_CREG_BLOCK 0x00

#define	WIZCHIP_SREG_BLOCK(N)

#define	WIZCHIP_TXBUF_BLOCK(N)

#define	WIZCHIP_RXBUF_BLOCK(N)

#define	WIZCHIP_OFFSET_INC(ADDR, N)

#define	IINCHIP_READ(ADDR)
	The defined for legacy chip driver.

#define	IINCHIP_WRITE(ADDR, VAL)
	The defined for legacy chip driver.

#define	IINCHIP_READ_BUF(ADDR, BUF, LEN)
	The defined for legacy chip driver.

#define	IINCHIP_WRITE_BUF(ADDR, BUF, LEN)
	The defined for legacy chip driver.

#define	MR (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_CREG_BLOCK << 3))
	Mode Register address(R/W) MR is used for S/W reset, ping block mode, PPPoE mode and etc.

#define	GAR (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_CREG_BLOCK << 3))
	Gateway IP Register address(R/W)

#define	SUBR (_W5500_IO_BASE_ + (0x0005 << 8) + (WIZCHIP_CREG_BLOCK << 3))
	Subnet mask Register address(R/W)

#define	SHAR (_W5500_IO_BASE_ + (0x0009 << 8) + (WIZCHIP_CREG_BLOCK << 3))
	Source MAC Register address(R/W)

#define	SIPR (_W5500_IO_BASE_ + (0x000F << 8) + (WIZCHIP_CREG_BLOCK << 3))
	Source IP Register address(R/W)

#define	INTLEVEL (_W5500_IO_BASE_ + (0x0013 << 8) + (WIZCHIP_CREG_BLOCK << 3))
	Set Interrupt low level timer register address(R/W)

#define	IR (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_CREG_BLOCK << 3))
	Interrupt Register(R/W)

#define	_IMR_ (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_CREG_BLOCK << 3))
	Interrupt mask register(R/W)

#define	SIR (_W5500_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_CREG_BLOCK << 3))
	Socket Interrupt Register(R/W)

#define	SIMR (_W5500_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_CREG_BLOCK << 3))
	Socket Interrupt Mask Register(R/W)

#define	_RTR_ (_W5500_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_CREG_BLOCK << 3))
	Timeout register address( 1 is 100us )(R/W)

#define	_RCR_ (_W5500_IO_BASE_ + (0x001B << 8) + (WIZCHIP_CREG_BLOCK << 3))
	Retry count register(R/W)

#define	PTIMER (_W5500_IO_BASE_ + (0x001C << 8) + (WIZCHIP_CREG_BLOCK << 3))
	PPP LCP Request Timer register in PPPoE mode(R/W)

#define	PMAGIC (_W5500_IO_BASE_ + (0x001D << 8) + (WIZCHIP_CREG_BLOCK << 3))
	PPP LCP Magic number register in PPPoE mode(R/W)

#define	PHAR (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_CREG_BLOCK << 3))
	PPP Destination MAC Register address(R/W)

#define	PSID (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_CREG_BLOCK << 3))
	PPP Session Identification Register(R/W)

#define	PMRU (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_CREG_BLOCK << 3))
	PPP Maximum Segment Size(MSS) register(R/W)

#define	UIPR (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_CREG_BLOCK << 3))
	Unreachable IP register address in UDP mode(R)

#define	UPORTR (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_CREG_BLOCK << 3))
	Unreachable Port register address in UDP mode(R)

#define	PHYCFGR (_W5500_IO_BASE_ + (0x002E << 8) + (WIZCHIP_CREG_BLOCK << 3))
	PHY Status Register(R/W)

#define	VERSIONR (_W5500_IO_BASE_ + (0x0039 << 8) + (WIZCHIP_CREG_BLOCK << 3))
	chip version register address(R)

#define	Sn_MR(N)
	socket Mode register(R/W)

#define	Sn_CR(N)
	Socket command register(R/W)

#define	Sn_IR(N)
	Socket interrupt register(R)

#define	Sn_SR(N)
	Socket status register(R)

#define	Sn_PORT(N)
	source port register(R/W)

#define	Sn_DHAR(N)
	Peer MAC register address(R/W)

#define	Sn_DIPR(N)
	Peer IP register address(R/W)

#define	Sn_DPORT(N)
	Peer port register address(R/W)

#define	Sn_MSSR(N)
	Maximum Segment Size(Sn_MSSR0) register address(R/W)

#define	Sn_TOS(N)
	IP Type of Service(TOS) Register(R/W)

#define	Sn_TTL(N)
	IP Time to live(TTL) Register(R/W)

#define	Sn_RXBUF_SIZE(N)
	Receive memory size register(R/W)

#define	Sn_TXBUF_SIZE(N)
	Transmit memory size register(R/W)

#define	Sn_TX_FSR(N)
	Transmit free memory size register(R)

#define	Sn_TX_RD(N)
	Transmit memory read pointer register address(R)

#define	Sn_TX_WR(N)
	Transmit memory write pointer register address(R/W)

#define	Sn_RX_RSR(N)
	Received data size register(R)

#define	Sn_RX_RD(N)
	Read point of Receive memory(R/W)

#define	Sn_RX_WR(N)
	Write point of Receive memory(R)

#define	Sn_IMR(N)
	socket interrupt mask register(R)

#define	Sn_FRAG(N)
	Fragment field value in IP header register(R/W)

#define	Sn_KPALVTR(N)
	Keep Alive Timer register(R/W)

#define	MR_RST 0x80
	Reset.

#define	MR_WOL 0x20
	Wake on LAN.

#define	MR_PB 0x10
	Ping block.

#define	MR_PPPOE 0x08
	Enable PPPoE.

#define	MR_FARP 0x02
	Enable UDP_FORCE_ARP CHECHK.

#define	IR_CONFLICT 0x80
	Check IP conflict.

#define	IR_UNREACH 0x40
	Get the destination unreachable message in UDP sending.

#define	IR_PPPoE 0x20
	Get the PPPoE close message.

#define	IR_MP 0x10
	Get the magic packet interrupt.

#define	PHYCFGR_RST ~(1 << 7)

#define	PHYCFGR_OPMD (1 << 6)

#define	PHYCFGR_OPMDC_ALLA (7 << 3)

#define	PHYCFGR_OPMDC_PDOWN (6 << 3)

#define	PHYCFGR_OPMDC_NA (5 << 3)

#define	PHYCFGR_OPMDC_100FA (4 << 3)

#define	PHYCFGR_OPMDC_100F (3 << 3)

#define	PHYCFGR_OPMDC_100H (2 << 3)

#define	PHYCFGR_OPMDC_10F (1 << 3)

#define	PHYCFGR_OPMDC_10H (0 << 3)

#define	PHYCFGR_DPX_FULL (1 << 2)

#define	PHYCFGR_DPX_HALF (0 << 2)

#define	PHYCFGR_SPD_100 (1 << 1)

#define	PHYCFGR_SPD_10 (0 << 1)

#define	PHYCFGR_LNK_ON (1 << 0)

#define	PHYCFGR_LNK_OFF (0 << 0)

#define	IM_IR7 0x80
	IP Conflict Interrupt Mask.

#define	IM_IR6 0x40
	Destination unreachable Interrupt Mask.

#define	IM_IR5 0x20
	PPPoE Close Interrupt Mask.

#define	IM_IR4 0x10
	Magic Packet Interrupt Mask.

#define	Sn_MR_MULTI 0x80
	Support UDP Multicasting.

#define	Sn_MR_BCASTB 0x40
	Broadcast block in UDP Multicasting.

#define	Sn_MR_ND 0x20
	No Delayed Ack(TCP), Multicast flag.

#define	Sn_MR_UCASTB 0x10
	Unicast Block in UDP Multicasting.

#define	Sn_MR_MACRAW 0x04
	MAC LAYER RAW SOCK.

#define	Sn_MR_IPRAW 0x03

#define	Sn_MR_UDP 0x02
	UDP.

#define	Sn_MR_TCP 0x01
	TCP.

#define	Sn_MR_CLOSE 0x00
	Unused socket.

#define	Sn_MR_MFEN Sn_MR_MULTI
	MAC filter enable in Sn_MR_MACRAW mode.

#define	Sn_MR_MMB Sn_MR_ND
	Multicast Blocking in Sn_MR_MACRAW mode.

#define	Sn_MR_MIP6B Sn_MR_UCASTB
	IPv6 packet Blocking in Sn_MR_MACRAW mode.

#define	Sn_MR_MC Sn_MR_ND
	IGMP version used in UDP mulitcasting.

#define	SOCK_STREAM Sn_MR_TCP
	For Berkeley Socket API.

#define	SOCK_DGRAM Sn_MR_UDP
	For Berkeley Socket API.

#define	Sn_CR_OPEN 0x01
	Initialize or open socket.

#define	Sn_CR_LISTEN 0x02
	Wait connection request in TCP mode(Server mode)

#define	Sn_CR_CONNECT 0x04
	Send connection request in TCP mode(Client mode)

#define	Sn_CR_DISCON 0x08
	Send closing request in TCP mode.

#define	Sn_CR_CLOSE 0x10
	Close socket.

#define	Sn_CR_SEND 0x20
	Update TX buffer pointer and send data.

#define	Sn_CR_SEND_MAC 0x21
	Send data with MAC address, so without ARP process.

#define	Sn_CR_SEND_KEEP 0x22
	Send keep alive message.

#define	Sn_CR_RECV 0x40
	Update RX buffer pointer and receive data.

#define	Sn_IR_SENDOK 0x10
	SEND_OK Interrupt.

#define	Sn_IR_TIMEOUT 0x08
	TIMEOUT Interrupt.

#define	Sn_IR_RECV 0x04
	RECV Interrupt.

#define	Sn_IR_DISCON 0x02
	DISCON Interrupt.

#define	Sn_IR_CON 0x01
	CON Interrupt.

#define	SOCK_CLOSED 0x00
	Closed.

#define	SOCK_INIT 0x13
	Initiate state.

#define	SOCK_LISTEN 0x14
	Listen state.

#define	SOCK_SYNSENT 0x15
	Connection state.

#define	SOCK_SYNRECV 0x16
	Connection state.

#define	SOCK_ESTABLISHED 0x17
	Success to connect.

#define	SOCK_FIN_WAIT 0x18
	Closing state.

#define	SOCK_CLOSING 0x1A
	Closing state.

#define	SOCK_TIME_WAIT 0x1B
	Closing state.

#define	SOCK_CLOSE_WAIT 0x1C
	Closing state.

#define	SOCK_LAST_ACK 0x1D
	Closing state.

#define	SOCK_UDP 0x22
	UDP socket.

#define	SOCK_IPRAW 0x32

#define	SOCK_MACRAW 0x42
	MAC raw mode socket.

#define	IPPROTO_IP 0

#define	IPPROTO_ICMP 1

#define	IPPROTO_IGMP 2

#define	IPPROTO_GGP 3

#define	IPPROTO_TCP 6

#define	IPPROTO_PUP 12

#define	IPPROTO_UDP 17

#define	IPPROTO_IDP 22

#define	IPPROTO_ND 77

#define	IPPROTO_RAW 255

#define	WIZCHIP_CRITICAL_ENTER()
	Enter a critical section.

#define	WIZCHIP_CRITICAL_EXIT()
	Exit a critical section.

#define	setMR(mr)
	Set Mode Register.

#define	getMR()
	Get Mode Register.

#define	setGAR(gar)
	Set gateway IP address.

#define	getGAR(gar)
	Get gateway IP address.

#define	setSUBR(subr)
	Set subnet mask address.

#define	getSUBR(subr)
	Get subnet mask address.

#define	setSHAR(shar)
	Set local MAC address.

#define	getSHAR(shar)
	Get local MAC address.

#define	setSIPR(sipr)
	Set local IP address.

#define	getSIPR(sipr)
	Get local IP address.

#define	setINTLEVEL(intlevel)
	Set INTLEVEL register.

#define	getINTLEVEL()
	Get INTLEVEL register.

#define	setIR(ir)
	Set IR register.

#define	getIR()
	Get IR register.

#define	setIMR(imr)
	Set _IMR_ register.

#define	getIMR()
	Get _IMR_ register.

#define	setSIR(sir)
	Set SIR register.

#define	getSIR()
	Get SIR register.

#define	setSIMR(simr)
	Set SIMR register.

#define	getSIMR()
	Get SIMR register.

#define	setRTR(rtr)
	Set _RTR_ register.

#define	getRTR()
	Get _RTR_ register.

#define	setRCR(rcr)
	Set _RCR_ register.

#define	getRCR()
	Get _RCR_ register.

#define	setPTIMER(ptimer)
	Set PTIMER register.

#define	getPTIMER()
	Get PTIMER register.

#define	setPMAGIC(pmagic)
	Set PMAGIC register.

#define	getPMAGIC()
	Get PMAGIC register.

#define	setPHAR(phar)
	Set PHAR address.

#define	getPHAR(phar)
	Get PHAR address.

#define	setPSID(psid)
	Set PSID register.

#define	getPSID()
	Get PSID register.

#define	setPMRU(pmru)
	Set PMRU register.

#define	getPMRU()
	Get PMRU register.

#define	getUIPR(uipr)
	Get unreachable IP address.

#define	getUPORTR()
	Get UPORTR register.

#define	setPHYCFGR(phycfgr)
	Set PHYCFGR register.

#define	getPHYCFGR()
	Get PHYCFGR register.

#define	getVERSIONR()
	Get VERSIONR register.

#define	setSn_MR(sn, mr)
	Set Sn_MR register.

#define	getSn_MR(sn)
	Get Sn_MR register.

#define	setSn_CR(sn, cr)
	Set Sn_CR register.

#define	getSn_CR(sn)
	Get Sn_CR register.

#define	setSn_IR(sn, ir)
	Set Sn_IR register.

#define	getSn_IR(sn)
	Get Sn_IR register.

#define	setSn_IMR(sn, imr)
	Set Sn_IMR register.

#define	getSn_IMR(sn)
	Get Sn_IMR register.

#define	getSn_SR(sn)
	Get Sn_SR register.

#define	setSn_PORT(sn, port)
	Set Sn_PORT register.

#define	getSn_PORT(sn)
	Get Sn_PORT register.

#define	setSn_DHAR(sn, dhar)
	Set Sn_DHAR register.

#define	getSn_DHAR(sn, dhar)
	Get Sn_MR register.

#define	setSn_DIPR(sn, dipr)
	Set Sn_DIPR register.

#define	getSn_DIPR(sn, dipr)
	Get Sn_DIPR register.

#define	setSn_DPORT(sn, dport)
	Set Sn_DPORT register.

#define	getSn_DPORT(sn)
	Get Sn_DPORT register.

#define	setSn_MSSR(sn, mss)
	Set Sn_MSSR register.

#define	getSn_MSSR(sn)
	Get Sn_MSSR register.

#define	setSn_TOS(sn, tos)
	Set Sn_TOS register.

#define	getSn_TOS(sn)
	Get Sn_TOS register.

#define	setSn_TTL(sn, ttl)
	Set Sn_TTL register.

#define	getSn_TTL(sn)
	Get Sn_TTL register.

#define	setSn_RXBUF_SIZE(sn, rxbufsize)
	Set Sn_RXBUF_SIZE register.

#define	getSn_RXBUF_SIZE(sn)
	Get Sn_RXBUF_SIZE register.

#define	setSn_TXBUF_SIZE(sn, txbufsize)
	Set Sn_TXBUF_SIZE register.

#define	getSn_TXBUF_SIZE(sn)
	Get Sn_TXBUF_SIZE register.

#define	getSn_TX_RD(sn)
	Get Sn_TX_RD register.

#define	setSn_TX_WR(sn, txwr)
	Set Sn_TX_WR register.

#define	getSn_TX_WR(sn)
	Get Sn_TX_WR register.

#define	setSn_RX_RD(sn, rxrd)
	Set Sn_RX_RD register.

#define	getSn_RX_RD(sn)
	Get Sn_RX_RD register.

#define	getSn_RX_WR(sn)
	Get Sn_RX_WR register.

#define	setSn_FRAG(sn, frag)
	Set Sn_FRAG register.

#define	getSn_FRAG(sn)
	Get Sn_FRAG register.

#define	setSn_KPALVTR(sn, kpalvt)
	Set Sn_KPALVTR register.

#define	getSn_KPALVTR(sn)
	Get Sn_KPALVTR register.

#define	getSn_RxMAX(sn)
	Socket_register_access_function.

#define	getSn_TxMAX(sn)
	Socket_register_access_function.

Functions
uint8_t	WIZCHIP_READ (uint32_t AddrSel)
	It reads 1 byte value from a register.

void	WIZCHIP_WRITE (uint32_t AddrSel, uint8_t wb)
	It writes 1 byte value to a register.

void	WIZCHIP_READ_BUF (uint32_t AddrSel, uint8_t *pBuf, uint16_t len)
	It reads sequence data from registers.

void	WIZCHIP_WRITE_BUF (uint32_t AddrSel, uint8_t *pBuf, uint16_t len)
	It writes sequence data to registers.

uint16_t	getSn_TX_FSR (uint8_t sn)
	Get Sn_TX_FSR register.

uint16_t	getSn_RX_RSR (uint8_t sn)
	Get Sn_RX_RSR register.

void	wiz_send_data (uint8_t sn, uint8_t *wizdata, uint16_t len)
	It copies data to internal TX memory.

void	wiz_recv_data (uint8_t sn, uint8_t *wizdata, uint16_t len)
	It copies data to your buffer from internal RX memory.

void	wiz_recv_ignore (uint8_t sn, uint16_t len)
	It discard the received data in RX memory.

Detailed Description

W5500 HAL Header File.

Version: 1.0.0

Date: 2013/10/21

Revision history: <2015/02/05> Notice The version history is not updated after this point. Download the latest version directly from GitHub. Please visit the our GitHub repository for ioLibrary. >> https://github.com/Wiznet/ioLibrary_Driver <2013/10/21> 1st Release

Author: MidnightCow

Copyright

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

* Redistributions of source code must retain the above copyright

notice, this list of conditions and the following disclaimer.

Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
Neither the name of the <ORGANIZATION> nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Macro Definition Documentation

◆ getSn_RxMAX

#define getSn_RxMAX ( sn )

Value:

(((uint16_t)getSn_RXBUF_SIZE(sn)) << 10)

getSn_RXBUF_SIZE

#define getSn_RXBUF_SIZE(sn)

Get Sn_RXBUF_SIZE register.

Definition w5500.h:1897

Socket_register_access_function.

Gets the max buffer size of socket sn passed as parameter.

Parameters

(uint8_t)sn Socket number. It should be 0 ~ 7.

Returns: uint16_t. Value of Socket n RX max buffer size.

◆ getSn_TxMAX

#define getSn_TxMAX ( sn )

Value:

(((uint16_t)getSn_TXBUF_SIZE(sn)) << 10)

getSn_TXBUF_SIZE

#define getSn_TXBUF_SIZE(sn)

Get Sn_TXBUF_SIZE register.

Definition w5500.h:1917

Socket_register_access_function.

Gets the max buffer size of socket sn passed as parameters.

Parameters

(uint8_t)sn Socket number. It should be 0 ~ 7.

Returns: uint16_t. Value of Socket n TX max buffer size.

◆ IINCHIP_READ

#define IINCHIP_READ ( ADDR )

Value:

WIZCHIP_READ(ADDR)

WIZCHIP_READ

uint8_t WIZCHIP_READ(uint32_t AddrSel)

It reads 1 byte value from a register.

Definition w5500.c:65

The defined for legacy chip driver.

◆ IINCHIP_READ_BUF

#define IINCHIP_READ_BUF	(	ADDR,
		BUF,
		LEN )

Value:

WIZCHIP_READ_BUF(ADDR, BUF, LEN)

WIZCHIP_READ_BUF

void WIZCHIP_READ_BUF(uint32_t AddrSel, uint8_t *pBuf, uint16_t len)

It reads sequence data from registers.

Definition w5500.c:125

The defined for legacy chip driver.

◆ IINCHIP_WRITE

#define IINCHIP_WRITE	(		ADDR,
			VAL )

Value:

WIZCHIP_WRITE(ADDR, VAL)

WIZCHIP_WRITE

void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb)

It writes 1 byte value to a register.

Definition w5500.c:95

The defined for legacy chip driver.

◆ IINCHIP_WRITE_BUF

#define IINCHIP_WRITE_BUF	(	ADDR,
		BUF,
		LEN )

Value:

WIZCHIP_WRITE(ADDR, BUF, LEN)

The defined for legacy chip driver.

◆ IM_IR4

#define IM_IR4 0x10

Magic Packet Interrupt Mask.

0: Disable Magic Packet Interrupt
1: Enable Magic Packet Interrupt

◆ IM_IR5

#define IM_IR5 0x20

PPPoE Close Interrupt Mask.

0: Disable PPPoE Close Interrupt
1: Enable PPPoE Close Interrupt

◆ IM_IR6

#define IM_IR6 0x40

Destination unreachable Interrupt Mask.

0: Disable Destination unreachable Interrupt
1: Enable Destination unreachable Interrupt

◆ IM_IR7

#define IM_IR7 0x80

IP Conflict Interrupt Mask.

0: Disable IP Conflict Interrupt
1: Enable IP Conflict Interrupt

◆ IR_CONFLICT

#define IR_CONFLICT 0x80

Check IP conflict.

Bit is set as when own source IP address is same with the sender IP address in the received ARP request.

◆ IR_MP

#define IR_MP 0x10

Get the magic packet interrupt.

When WOL mode is enabled and receives the magic packet over UDP, this bit is set.

◆ IR_PPPoE

#define IR_PPPoE 0x20

Get the PPPoE close message.

When PPPoE is disconnected during PPPoE mode, this bit is set.

◆ IR_UNREACH

#define IR_UNREACH 0x40

Get the destination unreachable message in UDP sending.

When receiving the ICMP (Destination port unreachable) packet, this bit is set as When this bit is Destination Information such as IP address and Port number may be checked with the corresponding UIPR & UPORTR.

◆ MR_FARP

#define MR_FARP 0x02

Enable UDP_FORCE_ARP CHECHK.

0 : Disable Force ARP mode
1 : Enable Force ARP mode
In Force ARP mode, It forces on sending ARP Request whenever data is sent.

◆ MR_PB

#define MR_PB 0x10

Ping block.

0 : Disable Ping block
1 : Enable Ping block
If the bit is it blocks the response to a ping request.

◆ MR_PPPOE

#define MR_PPPOE 0x08

Enable PPPoE.

0 : DisablePPPoE mode
1 : EnablePPPoE mode
If you use ADSL, this bit should be

◆ MR_RST

#define MR_RST 0x80

Reset.

If this bit is All internal registers will be initialized. It will be automatically cleared as after S/W reset.

◆ MR_WOL

#define MR_WOL 0x20

Wake on LAN.

0 : Disable WOL mode
1 : Enable WOL mode
If WOL mode is enabled and the received magic packet over UDP has been normally processed, the Interrupt PIN (INTn) asserts to low. When using WOL mode, the UDP Socket should be opened with any source port number. (Refer to Socket n Mode Register (Sn_MR) for opening Socket.)

Note: The magic packet over UDP supported by W5500 consists of 6 bytes synchronization stream (xFFFFFFFFFFFF and 16 times Target MAC address stream in UDP payload. The options such like password are ignored. You can use any UDP source port number for WOL mode.

◆ Sn_CR_CLOSE

#define Sn_CR_CLOSE 0x10

Close socket.

Sn_SR is changed to SOCK_CLOSED.

◆ Sn_CR_CONNECT

#define Sn_CR_CONNECT 0x04

Send connection request in TCP mode(Client mode)

To connect, a connect-request (SYN packet) is sent to TCP serverconfigured by Sn_DIPR & Sn_DPORT(destination address & port). If the connect-request is successful, the Sn_SR is changed to SOCK_ESTABLISHED and the Sn_IR(0) becomes

The connect-request fails in the following three cases.

When a ARPTO occurs (Sn_IR[3] = ) because destination hardware address is not acquired through the ARP-process.
When a SYN/ACK packet is not received and TCPTO (Sn_IR(3) = )
When a RST packet is received instead of a SYN/ACK packet. In these cases, Sn_SR is changed to SOCK_CLOSED.
Note
This is valid only in TCP mode and operates when Socket n acts as TCP client

◆ Sn_CR_DISCON

#define Sn_CR_DISCON 0x08

Send closing request in TCP mode.

Regardless of TCP serveror TCP client the DISCON command processes the disconnect-process (b>Active closeor Passive close.

Active close: it transmits disconnect-request(FIN packet) to the connected peer

Passive close: When FIN packet is received from peer, a FIN packet is replied back to the peer.

When the disconnect-process is successful (that is, FIN/ACK packet is received successfully), Sn_SR is changed to SOCK_CLOSED.
Otherwise, TCPTO occurs (='1') and then Sn_SR is changed to SOCK_CLOSED.

Note: Valid only in TCP mode.

◆ Sn_CR_LISTEN

#define Sn_CR_LISTEN 0x02

Wait connection request in TCP mode(Server mode)

This is valid only in TCP mode (Sn_MR(P3:P0) = Sn_MR_TCP). In this mode, Socket n operates as a TCP serverand waits for connection-request (SYN packet) from any TCP client The Sn_SR changes the state from SOCK_INIT to SOCKET_LISTEN. When a TCP clientconnection request is successfully established, the Sn_SR changes from SOCK_LISTEN to SOCK_ESTABLISHED and the Sn_IR(0) becomes But when a TCP clientconnection request is failed, Sn_IR(3) becomes and the status of Sn_SR changes to SOCK_CLOSED.

◆ Sn_CR_OPEN

#define Sn_CR_OPEN 0x01

Initialize or open socket.

Socket n is initialized and opened according to the protocol selected in Sn_MR(P3:P0). The table below shows the value of Sn_SR corresponding to Sn_MR.

Sn_MR (P[3:0])	Sn_SR
Sn_MR_CLOSE (000)
Sn_MR_TCP (001)	SOCK_INIT (0x13)
Sn_MR_UDP (010)	SOCK_UDP (0x22)
S0_MR_MACRAW (100)	SOCK_MACRAW (0x02)

◆ Sn_CR_RECV

#define Sn_CR_RECV 0x40

Update RX buffer pointer and receive data.

RECV completes the processing of the received data in Socket n RX Buffer by using a RX read pointer register (Sn_RX_RD).
For more details, refer to Socket n RX Received Size Register (Sn_RX_RSR), Socket n RX Write Pointer Register (Sn_RX_WR), and Socket n RX Read Pointer Register (Sn_RX_RD).

◆ Sn_CR_SEND

#define Sn_CR_SEND 0x20

Update TX buffer pointer and send data.

SEND transmits all the data in the Socket n TX buffer.
For more details, please refer to Socket n TX Free Size Register (Sn_TX_FSR), Socket n, TX Write Pointer Register(Sn_TX_WR), and Socket n TX Read Pointer Register(Sn_TX_RD).

◆ Sn_CR_SEND_KEEP

#define Sn_CR_SEND_KEEP 0x22

Send keep alive message.

It checks the connection status by sending 1byte keep-alive packet.
If the peer can not respond to the keep-alive packet during timeout time, the connection is terminated and the timeout interrupt will occur.

Note: Valid only in TCP mode.

◆ Sn_CR_SEND_MAC

#define Sn_CR_SEND_MAC 0x21

Send data with MAC address, so without ARP process.

The basic operation is same as SEND.
Normally SEND transmits data after destination hardware address is acquired by the automatic ARP-process(Address Resolution Protocol).
But SEND_MAC transmits data without the automatic ARP-process.
In this case, the destination hardware address is acquired from Sn_DHAR configured by host, instead of APR-process.

Note: Valid only in UDP mode.

◆ Sn_IR_CON

#define Sn_IR_CON 0x01

CON Interrupt.

This is issued one time when the connection with peer is successful and then Sn_SR is changed to SOCK_ESTABLISHED.

◆ Sn_IR_DISCON

#define Sn_IR_DISCON 0x02

DISCON Interrupt.

This is issued when FIN or FIN/ACK packet is received from a peer.

◆ Sn_IR_RECV

#define Sn_IR_RECV 0x04

RECV Interrupt.

This is issued whenever data is received from a peer.

◆ Sn_IR_SENDOK

#define Sn_IR_SENDOK 0x10

SEND_OK Interrupt.

This is issued when SEND command is completed.

◆ Sn_IR_TIMEOUT

#define Sn_IR_TIMEOUT 0x08

TIMEOUT Interrupt.

This is issued when ARPTO or TCPTO occurs.

◆ Sn_MR_BCASTB

#define Sn_MR_BCASTB 0x40

Broadcast block in UDP Multicasting.

0 : disable Broadcast Blocking
1 : enable Broadcast Blocking
This bit blocks to receive broadcasting packet during UDP mode(P[3:0] = 010.\m In addition, This bit does when MACRAW mode(P[3:0] = 100

◆ Sn_MR_CLOSE

#define Sn_MR_CLOSE 0x00

Unused socket.

This configures the protocol mode of Socket n.

◆ Sn_MR_IPRAW

#define Sn_MR_IPRAW 0x03

IP LAYER RAW SOCK

◆ Sn_MR_MACRAW

#define Sn_MR_MACRAW 0x04

MAC LAYER RAW SOCK.

This configures the protocol mode of Socket n.

Note: MACRAW mode should be only used in Socket 0.

◆ Sn_MR_MC

#define Sn_MR_MC Sn_MR_ND

IGMP version used in UDP mulitcasting.

0 : disable Multicast Blocking
1 : enable Multicast Blocking
This bit is applied only when MACRAW mode(P[3:0] = 100. It blocks to receive the packet with multicast MAC address.

◆ Sn_MR_MFEN

#define Sn_MR_MFEN Sn_MR_MULTI

MAC filter enable in Sn_MR_MACRAW mode.

0 : disable MAC Filtering
1 : enable MAC Filtering
This bit is applied only during MACRAW mode(P[3:0] = 100.
When set as W5500 can only receive broadcasting packet or packet sent to itself. When this bit is W5500 can receive all packets on Ethernet. If user wants to implement Hybrid TCP/IP stack, it is recommended that this bit is set as for reducing host overhead to process the all received packets.

◆ Sn_MR_MIP6B

#define Sn_MR_MIP6B Sn_MR_UCASTB

IPv6 packet Blocking in Sn_MR_MACRAW mode.

0 : disable IPv6 Blocking
1 : enable IPv6 Blocking
This bit is applied only during MACRAW mode (P[3:0] = 100. It blocks to receiving the IPv6 packet.

◆ Sn_MR_MMB

#define Sn_MR_MMB Sn_MR_ND

Multicast Blocking in Sn_MR_MACRAW mode.

0 : using IGMP version 2
1 : using IGMP version 1
This bit is applied only during UDP mode(P[3:0] = 010 and MULTI = It configures the version for IGMP messages (Join/Leave/Report).

◆ Sn_MR_MULTI

#define Sn_MR_MULTI 0x80

Support UDP Multicasting.

0 : disable Multicasting
1 : enable Multicasting
This bit is applied only during UDP mode(P[3:0] = 010.
To use multicasting, Sn_DIPR & Sn_DPORT should be respectively configured with the multicast group IP address & port number before Socket n is opened by OPEN command of Sn_CR.

◆ Sn_MR_ND

#define Sn_MR_ND 0x20

No Delayed Ack(TCP), Multicast flag.

0 : Disable No Delayed ACK option
1 : Enable No Delayed ACK option
This bit is applied only during TCP mode (P[3:0] = 001.
When this bit is It sends the ACK packet without delay as soon as a Data packet is received from a peer.
When this bit is It sends the ACK packet after waiting for the timeout time configured by _RTR_.

◆ Sn_MR_TCP

#define Sn_MR_TCP 0x01

TCP.

This configures the protocol mode of Socket n.

◆ Sn_MR_UCASTB

#define Sn_MR_UCASTB 0x10

Unicast Block in UDP Multicasting.

0 : disable Unicast Blocking
1 : enable Unicast Blocking
This bit blocks receiving the unicast packet during UDP mode(P[3:0] = 010 and MULTI =

◆ Sn_MR_UDP

#define Sn_MR_UDP 0x02

UDP.

This configures the protocol mode of Socket n.

◆ SOCK_CLOSE_WAIT

#define SOCK_CLOSE_WAIT 0x1C

Closing state.

This indicates Socket n received the disconnect-request (FIN packet) from the connected peer.
This is half-closing status, and data can be transferred.
For full-closing, DISCON command is used. But For just-closing, CLOSE command is used.

◆ SOCK_CLOSED

#define SOCK_CLOSED 0x00

Closed.

This indicates that Socket n is released.
When DICON, CLOSE command is ordered, or when a timeout occurs, it is changed to SOCK_CLOSED regardless of previous status.

◆ SOCK_CLOSING

#define SOCK_CLOSING 0x1A

Closing state.

These indicate Socket n is closing.
These are shown in disconnect-process such as active-close and passive-close.
When Disconnect-process is successfully completed, or when timeout occurs, these change to SOCK_CLOSED.

◆ SOCK_ESTABLISHED

#define SOCK_ESTABLISHED 0x17

Success to connect.

This indicates the status of the connection of Socket n.
It changes to SOCK_ESTABLISHED when the TCP SERVERprocessed the SYN packet from the TCP CLIENTduring SOCK_LISTEN, or when the CONNECT command is successful.
During SOCK_ESTABLISHED, DATA packet can be transferred using SEND or RECV command.

◆ SOCK_FIN_WAIT

#define SOCK_FIN_WAIT 0x18

Closing state.

These indicate Socket n is closing.
These are shown in disconnect-process such as active-close and passive-close.
When Disconnect-process is successfully completed, or when timeout occurs, these change to SOCK_CLOSED.

◆ SOCK_INIT

#define SOCK_INIT 0x13

Initiate state.

This indicates Socket n is opened with TCP mode.
It is changed to SOCK_INIT when Sn_MR(P[3:0]) = 001 and OPEN command is ordered.
After SOCK_INIT, user can use LISTEN /CONNECT command.

◆ SOCK_IPRAW

#define SOCK_IPRAW 0x32

IP raw mode socket

◆ SOCK_LAST_ACK

#define SOCK_LAST_ACK 0x1D

Closing state.

This indicates Socket n is waiting for the response (FIN/ACK packet) to the disconnect-request (FIN packet) by passive-close.
It changes to SOCK_CLOSED when Socket n received the response successfully, or when timeout(Sn_IR[TIMEOUT] = '1') is occurred.

◆ SOCK_LISTEN

#define SOCK_LISTEN 0x14

Listen state.

This indicates Socket n is operating as TCP servermode and waiting for connection-request (SYN packet) from a peer TCP client.
It will change to SOCK_ESTALBLISHED when the connection-request is successfully accepted.
Otherwise it will change to SOCK_CLOSED after TCPTO Sn_IR(TIMEOUT) = '1') is occurred.

◆ SOCK_MACRAW

#define SOCK_MACRAW 0x42

MAC raw mode socket.

This indicates Socket 0 is opened in MACRAW mode (S0_MR(P[3:0]) = 100and is valid only in Socket 0.
It changes to SOCK_MACRAW when S0_MR(P[3:0] = 100and OPEN command is ordered.
Like UDP mode socket, MACRAW mode Socket 0 can transfer a MAC packet (Ethernet frame) without the connection-process.

◆ SOCK_SYNRECV

#define SOCK_SYNRECV 0x16

Connection state.

It indicates Socket n successfully received the connect-request packet (SYN packet) from a peer.
If socket n sends the response (SYN/ACK packet) to the peer successfully, it changes to SOCK_ESTABLISHED.
If not, it changes to SOCK_CLOSED after timeout (Sn_IR[TIMEOUT] = '1') is occurred.

◆ SOCK_SYNSENT

#define SOCK_SYNSENT 0x15

Connection state.

This indicates Socket n sent the connect-request packet (SYN packet) to a peer.
It is temporarily shown when Sn_SR is changed from SOCK_INIT to SOCK_ESTABLISHED by CONNECT command.
If connect-accept(SYN/ACK packet) is received from the peer at SOCK_SYNSENT, it changes to SOCK_ESTABLISHED.
Otherwise, it changes to SOCK_CLOSED after TCPTO (Sn_IR[TIMEOUT] = '1') is occurred.

◆ SOCK_TIME_WAIT

#define SOCK_TIME_WAIT 0x1B

Closing state.

These indicate Socket n is closing.
These are shown in disconnect-process such as active-close and passive-close.
When Disconnect-process is successfully completed, or when timeout occurs, these change to SOCK_CLOSED.

◆ SOCK_UDP

#define SOCK_UDP 0x22

UDP socket.

This indicates Socket n is opened in UDP mode(Sn_MR(P[3:0]) = '010').
It changes to SOCK_UDP when Sn_MR(P[3:0]) = '010' and Sn_CR_OPEN command is ordered.
Unlike TCP mode, data can be transfered without the connection-process.

◆ WIZCHIP_CRITICAL_ENTER

#define WIZCHIP_CRITICAL_ENTER ( )

Value:

WIZCHIP.CRIS._enter()

WIZCHIP

_WIZCHIP WIZCHIP

Definition wizchip_conf.c:171

Enter a critical section.

It is provided to protect your shared code which are executed without distribution.

In non-OS environment, It can be just implemented by disabling whole interrupt.
In OS environment, You can replace it to critical section api supported by OS.

See also: WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF(); WIZCHIP_CRITICAL_EXIT()

◆ WIZCHIP_CRITICAL_EXIT

#define WIZCHIP_CRITICAL_EXIT ( )

Value:

WIZCHIP.CRIS._exit()

Exit a critical section.

It is provided to protect your shared code which are executed without distribution.

In non-OS environment, It can be just implemented by disabling whole interrupt.
In OS environment, You can replace it to critical section api supported by OS.

See also: WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF(); WIZCHIP_CRITICAL_ENTER()

◆ WIZCHIP_OFFSET_INC

#define WIZCHIP_OFFSET_INC	(		ADDR,
			N )

Value:

(ADDR + (N << 8))

◆ WIZCHIP_RXBUF_BLOCK

#define WIZCHIP_RXBUF_BLOCK ( N )

Value:

(3 + 4 * N)

◆ WIZCHIP_SREG_BLOCK

#define WIZCHIP_SREG_BLOCK ( N )

Value:

(1 + 4 * N)

◆ WIZCHIP_TXBUF_BLOCK

#define WIZCHIP_TXBUF_BLOCK ( N )

Value:

(2 + 4 * N)

Macros

Functions

Detailed Description

Macro Definition Documentation

◆ getSn_RxMAX

◆ getSn_TxMAX

◆ IINCHIP_READ

◆ IINCHIP_READ_BUF

◆ IINCHIP_WRITE

◆ IINCHIP_WRITE_BUF

◆ IM_IR4

◆ IM_IR5

◆ IM_IR6

◆ IM_IR7

◆ IR_CONFLICT

◆ IR_MP

◆ IR_PPPoE

◆ IR_UNREACH

◆ MR_FARP

◆ MR_PB

◆ MR_PPPOE

◆ MR_RST

◆ MR_WOL

◆ Sn_CR_CLOSE

◆ Sn_CR_CONNECT

◆ Sn_CR_DISCON

◆ Sn_CR_LISTEN

◆ Sn_CR_OPEN

◆ Sn_CR_RECV

◆ Sn_CR_SEND

◆ Sn_CR_SEND_KEEP

◆ Sn_CR_SEND_MAC

◆ Sn_IR_CON

◆ Sn_IR_DISCON

◆ Sn_IR_RECV

◆ Sn_IR_SENDOK

◆ Sn_IR_TIMEOUT

◆ Sn_MR_BCASTB

◆ Sn_MR_CLOSE

◆ Sn_MR_IPRAW

◆ Sn_MR_MACRAW

◆ Sn_MR_MC

◆ Sn_MR_MFEN

◆ Sn_MR_MIP6B

◆ Sn_MR_MMB

◆ Sn_MR_MULTI

◆ Sn_MR_ND

◆ Sn_MR_TCP

◆ Sn_MR_UCASTB

◆ Sn_MR_UDP

◆ SOCK_CLOSE_WAIT

◆ SOCK_CLOSED

◆ SOCK_CLOSING

◆ SOCK_ESTABLISHED

◆ SOCK_FIN_WAIT

◆ SOCK_INIT

◆ SOCK_IPRAW

◆ SOCK_LAST_ACK

◆ SOCK_LISTEN

◆ SOCK_MACRAW

◆ SOCK_SYNRECV

◆ SOCK_SYNSENT

◆ SOCK_TIME_WAIT

◆ SOCK_UDP

◆ WIZCHIP_CRITICAL_ENTER

◆ WIZCHIP_CRITICAL_EXIT

◆ WIZCHIP_OFFSET_INC

◆ WIZCHIP_RXBUF_BLOCK

◆ WIZCHIP_SREG_BLOCK

◆ WIZCHIP_TXBUF_BLOCK