dma_priv.h

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#ifndef PHAL_G4_DMA_PRIV_H
#define PHAL_G4_DMA_PRIV_H
 
#include "common/phal_G4/dma/dma.h"
 
 
// Every DMA1/DMA2 channel register block is this many bytes apart
// (RM0440 11: CCR, CNDTR, CPAR, CMAR, plus one reserved word = 20 bytes)
static constexpr uint32_t PHAL_DMA_PRIV_DMA_CHANNEL_MEM_STRIDE = 0x14U;
 
void PHAL_DMA_priv_enableClock(const DMA_TypeDef *periph);
 
DMA_Channel_TypeDef *PHAL_DMA_priv_getChannel(const DMA_TypeDef *periph, uint8_t channel_idx);
 
// Get the NVIC IRQn for (periph, channel_idx). channel_idx must be 1-8
IRQn_Type PHAL_DMA_priv_getIRQn(DMA_TypeDef *periph, uint8_t channel_idx);
 
void PHAL_DMA_priv_disableChannel(DMA_Channel_TypeDef *channel);
 
void PHAL_DMA_priv_enableChannel(DMA_Channel_TypeDef *channel);
 
bool PHAL_DMA_priv_isChannelEnabled(const DMA_Channel_TypeDef *channel);
 
void PHAL_DMA_priv_clearFlags(DMA_TypeDef *periph, uint8_t channel_idx);
 
void PHAL_DMA_priv_configChannel(DMA_Channel_TypeDef *channel,
                                 const PHAL_DMA_Wiring_t *wiring,
                                 const PHAL_DMA_Params_t *params);
 
void PHAL_DMA_priv_configMux(const PHAL_DMA_Wiring_t *wiring);
 
void PHAL_DMA_priv_setPeriphAddress(DMA_Channel_TypeDef *channel, uint32_t address);
 
void PHAL_DMA_priv_setMemAddress(DMA_Channel_TypeDef *channel, uint32_t address);
 
void PHAL_DMA_priv_setLength(DMA_Channel_TypeDef *channel, uint16_t length);
 
uint16_t PHAL_DMA_priv_getRemainingLength(DMA_Channel_TypeDef *channel);
 
bool PHAL_DMA_priv_readCompleteFlag(const DMA_TypeDef *periph, uint8_t channel_idx);
 
bool PHAL_DMA_priv_readErrorFlag(const DMA_TypeDef *periph, uint8_t channel_idx);
 
#endif // PHAL_G4_DMA_PRIV_H