dma_priv.h File Reference

G4 DMA Peripheral private/register level implementation. More...

#include "common/phal_G4/dma/dma.h"

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Functions
void	PHAL_DMA_priv_enableClock (const DMA_TypeDef *periph)
	Enable DMAMUX1's clock plus the given DMA peripheral's clock.
DMA_Channel_TypeDef *	PHAL_DMA_priv_getChannel (const DMA_TypeDef *periph, uint8_t channel_idx)
	Look up the channel instance for (periph, channel_idx). channel_idx must be 1-8.
IRQn_Type	PHAL_DMA_priv_getIRQn (DMA_TypeDef *periph, uint8_t channel_idx)
void	PHAL_DMA_priv_disableChannel (DMA_Channel_TypeDef *channel)
	Disable a channel and block until hardware confirms it is off.
void	PHAL_DMA_priv_enableChannel (DMA_Channel_TypeDef *channel)
	Enable a channel, starting its transfer.
bool	PHAL_DMA_priv_isChannelEnabled (const DMA_Channel_TypeDef *channel)
	True if the channel is currently enabled.
void	PHAL_DMA_priv_clearFlags (DMA_TypeDef *periph, uint8_t channel_idx)
	Clear every latched status flag (global/complete/half/error) for one channel.
void	PHAL_DMA_priv_configChannel (DMA_Channel_TypeDef *channel, const PHAL_DMA_Wiring_t *wiring, const PHAL_DMA_Params_t *params)
	Configure CCR (data sizes, priority, increment modes, mode, ISR enables) from wiring+params.
void	PHAL_DMA_priv_configMux (const PHAL_DMA_Wiring_t *wiring)
	Route wiring->mux_request to (periph, channel_idx)'s DMAMUX channel.
void	PHAL_DMA_priv_setPeriphAddress (DMA_Channel_TypeDef *channel, uint32_t address)
	Write the peripheral-side address (CPAR)
void	PHAL_DMA_priv_setMemAddress (DMA_Channel_TypeDef *channel, uint32_t address)
	Write the memory-side address (CMAR)
void	PHAL_DMA_priv_setLength (DMA_Channel_TypeDef *channel, uint16_t length)
	Write the transfer length (CNDTR)
uint16_t	PHAL_DMA_priv_getRemainingLength (DMA_Channel_TypeDef *channel)
	Read how many elements are still outstanding (CNDTR)
bool	PHAL_DMA_priv_readCompleteFlag (const DMA_TypeDef *periph, uint8_t channel_idx)
	True if the transfer-complete flag is currently set for (periph, channel_idx)
bool	PHAL_DMA_priv_readErrorFlag (const DMA_TypeDef *periph, uint8_t channel_idx)
	True if the transfer-error flag is currently set for (periph, channel_idx)

Variables
static constexpr uint32_t	PHAL_DMA_PRIV_DMA_CHANNEL_MEM_STRIDE = 0x14U

Detailed Description

G4 DMA Peripheral private/register level implementation.

Author

Shriya Balu (balu@.nosp@m.purd.nosp@m.ue.ed.nosp@m.u)

Millan Kumar (kumar.nosp@m.798@.nosp@m.purdu.nosp@m.e.ed.nosp@m.u)

Function Documentation

PHAL_DMA_priv_clearFlags()

void PHAL_DMA_priv_clearFlags	(	DMA_TypeDef *	periph,
		uint8_t	channel_idx )

Clear every latched status flag (global/complete/half/error) for one channel.

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PHAL_DMA_priv_configChannel()

void PHAL_DMA_priv_configChannel	(	DMA_Channel_TypeDef *	channel,
		const PHAL_DMA_Wiring_t *	wiring,
		const PHAL_DMA_Params_t *	params )

Configure CCR (data sizes, priority, increment modes, mode, ISR enables) from wiring+params.

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PHAL_DMA_priv_configMux()

void PHAL_DMA_priv_configMux

(

const PHAL_DMA_Wiring_t *

wiring

)

Route wiring->mux_request to (periph, channel_idx)'s DMAMUX channel.

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PHAL_DMA_priv_disableChannel()

void PHAL_DMA_priv_disableChannel

(

DMA_Channel_TypeDef *

channel

)

Disable a channel and block until hardware confirms it is off.

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PHAL_DMA_priv_enableChannel()

void PHAL_DMA_priv_enableChannel

(

DMA_Channel_TypeDef *

channel

)

Enable a channel, starting its transfer.

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PHAL_DMA_priv_enableClock()

void PHAL_DMA_priv_enableClock

(

const DMA_TypeDef *

periph

)

Enable DMAMUX1's clock plus the given DMA peripheral's clock.

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PHAL_DMA_priv_getChannel()

DMA_Channel_TypeDef * PHAL_DMA_priv_getChannel	(	const DMA_TypeDef *	periph,
		uint8_t	channel_idx )

Look up the channel instance for (periph, channel_idx). channel_idx must be 1-8.

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PHAL_DMA_priv_getIRQn()

IRQn_Type PHAL_DMA_priv_getIRQn	(	DMA_TypeDef *	periph,
		uint8_t	channel_idx )

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PHAL_DMA_priv_getRemainingLength()

uint16_t PHAL_DMA_priv_getRemainingLength

(

DMA_Channel_TypeDef *

channel

)

Read how many elements are still outstanding (CNDTR)

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PHAL_DMA_priv_isChannelEnabled()

bool PHAL_DMA_priv_isChannelEnabled

(

const DMA_Channel_TypeDef *

channel

)

True if the channel is currently enabled.

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PHAL_DMA_priv_readCompleteFlag()

bool PHAL_DMA_priv_readCompleteFlag	(	const DMA_TypeDef *	periph,
		uint8_t	channel_idx )

True if the transfer-complete flag is currently set for (periph, channel_idx)

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PHAL_DMA_priv_readErrorFlag()

bool PHAL_DMA_priv_readErrorFlag	(	const DMA_TypeDef *	periph,
		uint8_t	channel_idx )

True if the transfer-error flag is currently set for (periph, channel_idx)

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PHAL_DMA_priv_setLength()

void PHAL_DMA_priv_setLength	(	DMA_Channel_TypeDef *	channel,
		uint16_t	length )

Write the transfer length (CNDTR)

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PHAL_DMA_priv_setMemAddress()

void PHAL_DMA_priv_setMemAddress	(	DMA_Channel_TypeDef *	channel,
		uint32_t	address )

Write the memory-side address (CMAR)

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PHAL_DMA_priv_setPeriphAddress()

void PHAL_DMA_priv_setPeriphAddress	(	DMA_Channel_TypeDef *	channel,
		uint32_t	address )

Write the peripheral-side address (CPAR)

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Variable Documentation

PHAL_DMA_PRIV_DMA_CHANNEL_MEM_STRIDE

uint32_t PHAL_DMA_PRIV_DMA_CHANNEL_MEM_STRIDE = 0x14U

staticconstexpr