dma_wiring.h File Reference

G4 DMA Peripheral wiring configuration and definitions. More...

#include "stm32g474xx.h"

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Classes
struct	PHAL_DMA_Wiring_t
	Fixed hardware wiring for one peripheral + direction's DMA use. More...

Enumerations
enum	PHAL_DMA_Size_t { DMA_SIZE_8BIT = 0 , DMA_SIZE_16BIT = 1 , DMA_SIZE_32BIT = 2 }
	Width of each DMA data element. More...
enum	PHAL_DMA_Direction_t { DMA_PERIPH_TO_MEMORY = 0 , DMA_MEMORY_TO_PERIPH = 1 }
	Direction of a peripheral <-> memory transfer. More...
enum	PHAL_DMA_Request_t : uint8_t {   DMA_REQUEST_ADC1 = 5U , DMA_REQUEST_ADC2 = 36U , DMA_REQUEST_ADC3 = 37U , DMA_REQUEST_ADC4 = 38U ,   DMA_REQUEST_SPI1_RX = 10U , DMA_REQUEST_SPI1_TX = 11U , DMA_REQUEST_SPI2_RX = 12U , DMA_REQUEST_SPI2_TX = 13U ,   DMA_REQUEST_SPI3_RX = 14U , DMA_REQUEST_SPI3_TX = 15U , DMA_REQUEST_USART1_RX = 24U , DMA_REQUEST_USART1_TX = 25U ,   DMA_REQUEST_USART2_RX = 26U , DMA_REQUEST_USART2_TX = 27U , DMA_REQUEST_USART3_RX = 28U , DMA_REQUEST_USART3_TX = 29U }
	DMAMUX request IDs (RM0440 Table 91) More...

Variables
static const PHAL_DMA_Wiring_t	USART1_RX_DMA_WIRING
static const PHAL_DMA_Wiring_t	USART1_TX_DMA_WIRING
static const PHAL_DMA_Wiring_t	USART2_RX_DMA_WIRING
static const PHAL_DMA_Wiring_t	USART2_TX_DMA_WIRING
static const PHAL_DMA_Wiring_t	USART3_RX_DMA_WIRING
static const PHAL_DMA_Wiring_t	USART3_TX_DMA_WIRING
static const PHAL_DMA_Wiring_t	SPI1_RX_DMA_WIRING
static const PHAL_DMA_Wiring_t	SPI1_TX_DMA_WIRING
static const PHAL_DMA_Wiring_t	SPI2_RX_DMA_WIRING
static const PHAL_DMA_Wiring_t	SPI2_TX_DMA_WIRING
static const PHAL_DMA_Wiring_t	SPI3_RX_DMA_WIRING
static const PHAL_DMA_Wiring_t	SPI3_TX_DMA_WIRING
static const PHAL_DMA_Wiring_t	ADC1_DMA_WIRING
static const PHAL_DMA_Wiring_t	ADC2_DMA_WIRING
static const PHAL_DMA_Wiring_t	ADC3_DMA_WIRING
static const PHAL_DMA_Wiring_t	ADC4_DMA_WIRING

Detailed Description

G4 DMA Peripheral wiring configuration and definitions.

Author

Millan Kumar (kumar.nosp@m.798@.nosp@m.purdu.nosp@m.e.ed.nosp@m.u)

Enumeration Type Documentation

PHAL_DMA_Direction_t

enum PHAL_DMA_Direction_t

Direction of a peripheral <-> memory transfer.

Ignored for DMA_MODE_MEM2MEM, which moves data between two memory addresses with no peripheral or DMAMUX request involved.

Enumerator
DMA_PERIPH_TO_MEMORY
DMA_MEMORY_TO_PERIPH

PHAL_DMA_Request_t

enum PHAL_DMA_Request_t : uint8_t

DMAMUX request IDs (RM0440 Table 91)

Not every peripheral is listed yet

Enumerator
DMA_REQUEST_ADC1
DMA_REQUEST_ADC2
DMA_REQUEST_ADC3
DMA_REQUEST_ADC4
DMA_REQUEST_SPI1_RX
DMA_REQUEST_SPI1_TX
DMA_REQUEST_SPI2_RX
DMA_REQUEST_SPI2_TX
DMA_REQUEST_SPI3_RX
DMA_REQUEST_SPI3_TX
DMA_REQUEST_USART1_RX
DMA_REQUEST_USART1_TX
DMA_REQUEST_USART2_RX
DMA_REQUEST_USART2_TX
DMA_REQUEST_USART3_RX
DMA_REQUEST_USART3_TX

PHAL_DMA_Size_t

enum PHAL_DMA_Size_t

Width of each DMA data element.

Enumerator
DMA_SIZE_8BIT
DMA_SIZE_16BIT
DMA_SIZE_32BIT

Variable Documentation

ADC1_DMA_WIRING

const PHAL_DMA_Wiring_t ADC1_DMA_WIRING

static

Initial value:

= {
    .periph      = DMA1,
    .channel_idx = 1,
    .mux_request = DMA_REQUEST_ADC1,
    .periph_reg  = &ADC1->DR,
    .dir         = DMA_PERIPH_TO_MEMORY,
    .data_size   = DMA_SIZE_16BIT,
}

ADC2_DMA_WIRING

const PHAL_DMA_Wiring_t ADC2_DMA_WIRING

static

Initial value:

= {
    .periph      = DMA2,
    .channel_idx = 1,
    .mux_request = DMA_REQUEST_ADC2,
    .periph_reg  = &ADC2->DR,
    .dir         = DMA_PERIPH_TO_MEMORY,
    .data_size   = DMA_SIZE_16BIT,
}

ADC3_DMA_WIRING

const PHAL_DMA_Wiring_t ADC3_DMA_WIRING

static

Initial value:

= {
    .periph      = DMA2,
    .channel_idx = 2,
    .mux_request = DMA_REQUEST_ADC3,
    .periph_reg  = &ADC3->DR,
    .dir         = DMA_PERIPH_TO_MEMORY,
    .data_size   = DMA_SIZE_16BIT,
}

ADC4_DMA_WIRING

const PHAL_DMA_Wiring_t ADC4_DMA_WIRING

static

Initial value:

= {
    .periph      = DMA2,
    .channel_idx = 3,
    .mux_request = DMA_REQUEST_ADC4,
    .periph_reg  = &ADC4->DR,
    .dir         = DMA_PERIPH_TO_MEMORY,
    .data_size   = DMA_SIZE_16BIT,
}

SPI1_RX_DMA_WIRING

const PHAL_DMA_Wiring_t SPI1_RX_DMA_WIRING

static

Initial value:

= {
    .periph      = DMA1,
    .channel_idx = 2,
    .mux_request = DMA_REQUEST_SPI1_RX,
    .periph_reg  = &SPI1->DR,
    .dir         = DMA_PERIPH_TO_MEMORY,
    .data_size   = DMA_SIZE_8BIT,
}

SPI1_TX_DMA_WIRING

const PHAL_DMA_Wiring_t SPI1_TX_DMA_WIRING

static

Initial value:

= {
    .periph      = DMA1,
    .channel_idx = 3,
    .mux_request = DMA_REQUEST_SPI1_TX,
    .periph_reg  = &SPI1->DR,
    .dir         = DMA_MEMORY_TO_PERIPH,
    .data_size   = DMA_SIZE_8BIT,
}

SPI2_RX_DMA_WIRING

const PHAL_DMA_Wiring_t SPI2_RX_DMA_WIRING

static

Initial value:

= {
    .periph      = DMA1,
    .channel_idx = 4,
    .mux_request = DMA_REQUEST_SPI2_RX,
    .periph_reg  = &SPI2->DR,
    .dir         = DMA_PERIPH_TO_MEMORY,
    .data_size   = DMA_SIZE_8BIT,
}

SPI2_TX_DMA_WIRING

const PHAL_DMA_Wiring_t SPI2_TX_DMA_WIRING

static

Initial value:

= {
    .periph      = DMA1,
    .channel_idx = 5,
    .mux_request = DMA_REQUEST_SPI2_TX,
    .periph_reg  = &SPI2->DR,
    .dir         = DMA_MEMORY_TO_PERIPH,
    .data_size   = DMA_SIZE_8BIT,
}

SPI3_RX_DMA_WIRING

const PHAL_DMA_Wiring_t SPI3_RX_DMA_WIRING

static

Initial value:

= {
    .periph      = DMA2,
    .channel_idx = 2,
    .mux_request = DMA_REQUEST_SPI3_RX,
    .periph_reg  = &SPI3->DR,
    .dir         = DMA_PERIPH_TO_MEMORY,
    .data_size   = DMA_SIZE_8BIT,
}

SPI3_TX_DMA_WIRING

const PHAL_DMA_Wiring_t SPI3_TX_DMA_WIRING

static

Initial value:

= {
    .periph      = DMA2,
    .channel_idx = 3,
    .mux_request = DMA_REQUEST_SPI3_TX,
    .periph_reg  = &SPI3->DR,
    .dir         = DMA_MEMORY_TO_PERIPH,
    .data_size   = DMA_SIZE_8BIT,
}

USART1_RX_DMA_WIRING

const PHAL_DMA_Wiring_t USART1_RX_DMA_WIRING

static

Initial value:

= {
    .periph      = DMA1,
    .channel_idx = 5,
    .mux_request = DMA_REQUEST_USART1_RX,
    .periph_reg  = &USART1->RDR,
    .dir         = DMA_PERIPH_TO_MEMORY,
    .data_size   = DMA_SIZE_8BIT,
}

USART1_TX_DMA_WIRING

const PHAL_DMA_Wiring_t USART1_TX_DMA_WIRING

static

Initial value:

= {
    .periph      = DMA1,
    .channel_idx = 7,
    .mux_request = DMA_REQUEST_USART1_TX,
    .periph_reg  = &USART1->TDR,
    .dir         = DMA_MEMORY_TO_PERIPH,
    .data_size   = DMA_SIZE_8BIT,
}

USART2_RX_DMA_WIRING

const PHAL_DMA_Wiring_t USART2_RX_DMA_WIRING

static

Initial value:

= {
    .periph      = DMA1,
    .channel_idx = 3,
    .mux_request = DMA_REQUEST_USART2_RX,
    .periph_reg  = &USART2->RDR,
    .dir         = DMA_PERIPH_TO_MEMORY,
    .data_size   = DMA_SIZE_8BIT,
}

USART2_TX_DMA_WIRING

const PHAL_DMA_Wiring_t USART2_TX_DMA_WIRING

static

Initial value:

= {
    .periph      = DMA1,
    .channel_idx = 4,
    .mux_request = DMA_REQUEST_USART2_TX,
    .periph_reg  = &USART2->TDR,
    .dir         = DMA_MEMORY_TO_PERIPH,
    .data_size   = DMA_SIZE_8BIT,
}

USART3_RX_DMA_WIRING

const PHAL_DMA_Wiring_t USART3_RX_DMA_WIRING

static

Initial value:

= {
    .periph      = DMA1,
    .channel_idx = 1,
    .mux_request = DMA_REQUEST_USART3_RX,
    .periph_reg  = &USART3->RDR,
    .dir         = DMA_PERIPH_TO_MEMORY,
    .data_size   = DMA_SIZE_8BIT,
}

USART3_TX_DMA_WIRING

const PHAL_DMA_Wiring_t USART3_TX_DMA_WIRING

static

Initial value:

= {
    .periph      = DMA1,
    .channel_idx = 2,
    .mux_request = DMA_REQUEST_USART3_TX,
    .periph_reg  = &USART3->TDR,
    .dir         = DMA_MEMORY_TO_PERIPH,
    .data_size   = DMA_SIZE_8BIT,
}