fdcan_priv.h

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#ifndef PHAL_G4_FDCAN_PRIV_H
#define PHAL_G4_FDCAN_PRIV_H
 
#include <stdint.h>
 
#include "stm32g474xx.h"
 
 
static constexpr uint32_t FDCAN_PRIV_KER_CLK_HZ = 16'000'000U;
 
// Values originate from ST's HAL & documentation
 
static constexpr uint32_t FDCAN_PRIV_RCC_FDCANCLKSOURCE_PCLK1 = RCC_CCIPR_FDCANSEL_1;
 
typedef enum : uint32_t {
    FDCAN_PRIV_FILTER_ACCEPT_IN_RX_FIFO0 = 0x00000000U,
    FDCAN_PRIV_FILTER_REJECT             = 0x00000002U
} PHAL_FDCAN_DefaultFilterAction_t;
 
// Message RAM layout. Same layout, different base offset for each peripheral
 
static constexpr uint32_t FDCAN_PRIV_SRAMCAN_FLS_NBR = 28; 
static constexpr uint32_t FDCAN_PRIV_SRAMCAN_FLE_NBR = 8;  
static constexpr uint32_t FDCAN_PRIV_SRAMCAN_RF0_NBR = 3;  
static constexpr uint32_t FDCAN_PRIV_SRAMCAN_RF1_NBR = 3;  
static constexpr uint32_t FDCAN_PRIV_SRAMCAN_TEF_NBR = 3;  
static constexpr uint32_t FDCAN_PRIV_SRAMCAN_TFQ_NBR = 3;  
 
static constexpr uint32_t FDCAN_PRIV_SRAMCAN_FLS_SIZE = 1 * 4;  // Filter Standard Element Size in bytes
static constexpr uint32_t FDCAN_PRIV_SRAMCAN_FLE_SIZE = 2 * 4;  // Filter Extended Element Size in bytes
 
static constexpr uint32_t FDCAN_PRIV_SRAMCAN_RF0_SIZE = 18 * 4;
 
static constexpr uint32_t FDCAN_PRIV_SRAMCAN_RF1_SIZE = 18 * 4; // RX FIFO 1 Elements Size in bytes
static constexpr uint32_t FDCAN_PRIV_SRAMCAN_TEF_SIZE = 2 * 4;  // TX Event FIFO Elements Size in bytes
 
static constexpr uint32_t FDCAN_PRIV_SRAMCAN_TFQ_SIZE = 18 * 4;
 
static constexpr uint32_t FDCAN_PRIV_SRAMCAN_FLSSA = 0;
 
static constexpr uint32_t FDCAN_PRIV_SRAMCAN_FLESA = FDCAN_PRIV_SRAMCAN_FLSSA + FDCAN_PRIV_SRAMCAN_FLS_NBR * FDCAN_PRIV_SRAMCAN_FLS_SIZE;
 
static constexpr uint32_t FDCAN_PRIV_SRAMCAN_RF0SA = FDCAN_PRIV_SRAMCAN_FLESA + FDCAN_PRIV_SRAMCAN_FLE_NBR * FDCAN_PRIV_SRAMCAN_FLE_SIZE;
static constexpr uint32_t FDCAN_PRIV_SRAMCAN_RF1SA = FDCAN_PRIV_SRAMCAN_RF0SA + FDCAN_PRIV_SRAMCAN_RF0_NBR * FDCAN_PRIV_SRAMCAN_RF0_SIZE;
static constexpr uint32_t FDCAN_PRIV_SRAMCAN_TEFSA = FDCAN_PRIV_SRAMCAN_RF1SA + FDCAN_PRIV_SRAMCAN_RF1_NBR * FDCAN_PRIV_SRAMCAN_RF1_SIZE;
 
static constexpr uint32_t FDCAN_PRIV_SRAMCAN_TFQSA = FDCAN_PRIV_SRAMCAN_TEFSA + FDCAN_PRIV_SRAMCAN_TEF_NBR * FDCAN_PRIV_SRAMCAN_TEF_SIZE;
 
static constexpr uint32_t FDCAN_PRIV_SRAMCAN_SIZE  = FDCAN_PRIV_SRAMCAN_TFQSA + FDCAN_PRIV_SRAMCAN_TFQ_NBR * FDCAN_PRIV_SRAMCAN_TFQ_SIZE;
 
 
uint32_t PHAL_FDCAN_priv_ramBase(const FDCAN_GlobalTypeDef *fdcan);
 
void PHAL_FDCAN_priv_enableClock(void);
 
void PHAL_FDCAN_priv_enterConfig(FDCAN_GlobalTypeDef *fdcan);
 
void PHAL_FDCAN_priv_exitConfig(FDCAN_GlobalTypeDef *fdcan);
 
// Configure CCCR and TEST registers for classic CAN operation
// Not FD, not BRS, not loopback, auto-retransmission enabled, TX pause on
void PHAL_FDCAN_priv_controlConfig(FDCAN_GlobalTypeDef *fdcan);
 
void PHAL_FDCAN_priv_setTransmitFifoQueueModeToFifo(FDCAN_GlobalTypeDef *fdcan);
 
void PHAL_FDCAN_setInterruptLines(FDCAN_GlobalTypeDef *fdcan);
 
void PHAL_FDCAN_priv_writeFilterAction(FDCAN_GlobalTypeDef *fdcan, PHAL_FDCAN_DefaultFilterAction_t action);
 
uint32_t PHAL_FDCAN_priv_getNBTP(PHAL_FDCAN_BaudRate_t bit_rate);
 
void PHAL_FDCAN_priv_writeStandardFilters(FDCAN_GlobalTypeDef *fdcan, const uint32_t *sid_list, uint32_t num_sid);
 
void PHAL_FDCAN_priv_writeExtendedFilters(FDCAN_GlobalTypeDef *fdcan, const uint32_t *xid_list, uint32_t num_xid);
 
void PHAL_FDCAN_priv_writeTxElement(FDCAN_GlobalTypeDef *fdcan, CanMsgTypeDef_t *msg);
 
// return true and fills msg on success. False if RX FIFO0 is empty
bool PHAL_FDCAN_priv_readRxElement(FDCAN_GlobalTypeDef *fdcan, CanMsgTypeDef_t *msg);
 
bool PHAL_FDCAN_priv_readTxFifoQueueStatusFullFlag(const FDCAN_GlobalTypeDef *fdcan);
 
bool PHAL_FDCAN_priv_readReceiveFifo0NewMessageInterruptFlag(const FDCAN_GlobalTypeDef *fdcan);
 
void PHAL_FDCAN_priv_clearReceiveFifo0NewMessageInterruptFlag(FDCAN_GlobalTypeDef *fdcan);
 
bool PHAL_FDCAN_priv_readTransmitCompleteInterruptFlag(const FDCAN_GlobalTypeDef *fdcan);
 
void PHAL_FDCAN_priv_clearTransmitCompleteInterruptFlag(FDCAN_GlobalTypeDef *fdcan);
 
#endif // PHAL_G4_FDCAN_PRIV_H