fdcan_priv.h File Reference

G4 FDCAN private/register level implementation. More...

#include <stdint.h>
#include "stm32g474xx.h"

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Enumerations
enum	PHAL_FDCAN_DefaultFilterAction_t : uint32_t { FDCAN_PRIV_FILTER_ACCEPT_IN_RX_FIFO0 = 0x00000000U , FDCAN_PRIV_FILTER_REJECT = 0x00000002U }

Functions
uint32_t	PHAL_FDCAN_priv_ramBase (const FDCAN_GlobalTypeDef *fdcan)
	Base address of this peripheral's slice of shared message RAM.
void	PHAL_FDCAN_priv_enableClock (void)
	Enable FDCAN kernel + peripheral clocks (PCLK1)
void	PHAL_FDCAN_priv_enterConfig (FDCAN_GlobalTypeDef *fdcan)
	Enter INIT mode and unlock configuration registers. Blocks until entered.
void	PHAL_FDCAN_priv_exitConfig (FDCAN_GlobalTypeDef *fdcan)
	Leave INIT mode, ending configuration. Blocks until left.
void	PHAL_FDCAN_priv_controlConfig (FDCAN_GlobalTypeDef *fdcan)
void	PHAL_FDCAN_priv_setTransmitFifoQueueModeToFifo (FDCAN_GlobalTypeDef *fdcan)
	Set TX FIFO/Queue mode to FIFO (not queue)
void	PHAL_FDCAN_setInterruptLines (FDCAN_GlobalTypeDef *fdcan)
	Set up RX new message -> line 0, TX complete -> line 1.
void	PHAL_FDCAN_priv_writeFilterAction (FDCAN_GlobalTypeDef *fdcan, PHAL_FDCAN_DefaultFilterAction_t action)
	Write a filter action to RXGFC (accept/reject all)
uint32_t	PHAL_FDCAN_priv_getNBTP (PHAL_FDCAN_BaudRate_t bit_rate)
void	PHAL_FDCAN_priv_writeStandardFilters (FDCAN_GlobalTypeDef *fdcan, const uint32_t *sid_list, uint32_t num_sid)
	Set num_sid exact-match standard filters and forward to RX FIFO0.
void	PHAL_FDCAN_priv_writeExtendedFilters (FDCAN_GlobalTypeDef *fdcan, const uint32_t *xid_list, uint32_t num_xid)
	Set num_xid exact-match extended filters and forward to RX FIFO0.
void	PHAL_FDCAN_priv_writeTxElement (FDCAN_GlobalTypeDef *fdcan, CanMsgTypeDef_t *msg)
bool	PHAL_FDCAN_priv_readRxElement (FDCAN_GlobalTypeDef *fdcan, CanMsgTypeDef_t *msg)
	Pop and decode the oldest element from RX FIFO0.
bool	PHAL_FDCAN_priv_readTxFifoQueueStatusFullFlag (const FDCAN_GlobalTypeDef *fdcan)
	Check whether the TX FIFO/Queue is full.
bool	PHAL_FDCAN_priv_readReceiveFifo0NewMessageInterruptFlag (const FDCAN_GlobalTypeDef *fdcan)
	Check whether the RX FIFO0 new message interrupt flag is set.
void	PHAL_FDCAN_priv_clearReceiveFifo0NewMessageInterruptFlag (FDCAN_GlobalTypeDef *fdcan)
	Clear the RX FIFO0 new message interrupt flag.
bool	PHAL_FDCAN_priv_readTransmitCompleteInterruptFlag (const FDCAN_GlobalTypeDef *fdcan)
	Check whether the TX complete interrupt flag is set.
void	PHAL_FDCAN_priv_clearTransmitCompleteInterruptFlag (FDCAN_GlobalTypeDef *fdcan)
	Clear the TX complete interrupt flag.

Variables
static constexpr uint32_t	FDCAN_PRIV_KER_CLK_HZ = 16'000'000U
static constexpr uint32_t	FDCAN_PRIV_RCC_FDCANCLKSOURCE_PCLK1 = RCC_CCIPR_FDCANSEL_1
	FDCAN clock is derived from PCLK1.
static constexpr uint32_t	FDCAN_PRIV_SRAMCAN_FLS_NBR = 28
static constexpr uint32_t	FDCAN_PRIV_SRAMCAN_FLE_NBR = 8
	Max standard id filters.
static constexpr uint32_t	FDCAN_PRIV_SRAMCAN_RF0_NBR = 3
	Max extended id filters.
static constexpr uint32_t	FDCAN_PRIV_SRAMCAN_RF1_NBR = 3
	RX FIFO 0 Elements Number.
static constexpr uint32_t	FDCAN_PRIV_SRAMCAN_TEF_NBR = 3
	RX FIFO 1 Elements Number.
static constexpr uint32_t	FDCAN_PRIV_SRAMCAN_TFQ_NBR = 3
	TX Event FIFO Elements Number.
static constexpr uint32_t	FDCAN_PRIV_SRAMCAN_FLS_SIZE = 1 * 4
	TX FIFO Elements Number.
static constexpr uint32_t	FDCAN_PRIV_SRAMCAN_FLE_SIZE = 2 * 4
static constexpr uint32_t	FDCAN_PRIV_SRAMCAN_RF0_SIZE = 18 * 4
	Size in bytes of one RX FIFO 0 element (set by the hardware format)
static constexpr uint32_t	FDCAN_PRIV_SRAMCAN_RF1_SIZE = 18 * 4
static constexpr uint32_t	FDCAN_PRIV_SRAMCAN_TEF_SIZE = 2 * 4
static constexpr uint32_t	FDCAN_PRIV_SRAMCAN_TFQ_SIZE = 18 * 4
	Size in bytes of one TX FIFO/queue element (set by the hardware format)
static constexpr uint32_t	FDCAN_PRIV_SRAMCAN_FLSSA = 0
static constexpr uint32_t	FDCAN_PRIV_SRAMCAN_FLESA = FDCAN_PRIV_SRAMCAN_FLSSA + FDCAN_PRIV_SRAMCAN_FLS_NBR * FDCAN_PRIV_SRAMCAN_FLS_SIZE
static constexpr uint32_t	FDCAN_PRIV_SRAMCAN_RF0SA = FDCAN_PRIV_SRAMCAN_FLESA + FDCAN_PRIV_SRAMCAN_FLE_NBR * FDCAN_PRIV_SRAMCAN_FLE_SIZE
static constexpr uint32_t	FDCAN_PRIV_SRAMCAN_RF1SA = FDCAN_PRIV_SRAMCAN_RF0SA + FDCAN_PRIV_SRAMCAN_RF0_NBR * FDCAN_PRIV_SRAMCAN_RF0_SIZE
static constexpr uint32_t	FDCAN_PRIV_SRAMCAN_TEFSA = FDCAN_PRIV_SRAMCAN_RF1SA + FDCAN_PRIV_SRAMCAN_RF1_NBR * FDCAN_PRIV_SRAMCAN_RF1_SIZE
static constexpr uint32_t	FDCAN_PRIV_SRAMCAN_TFQSA = FDCAN_PRIV_SRAMCAN_TEFSA + FDCAN_PRIV_SRAMCAN_TEF_NBR * FDCAN_PRIV_SRAMCAN_TEF_SIZE
static constexpr uint32_t	FDCAN_PRIV_SRAMCAN_SIZE = FDCAN_PRIV_SRAMCAN_TFQSA + FDCAN_PRIV_SRAMCAN_TFQ_NBR * FDCAN_PRIV_SRAMCAN_TFQ_SIZE
	Bytes required/consumed by one instance's full Message RAM layout (filters + RX FIFOs + TX event FIFO + TX FIFO)

Detailed Description

G4 FDCAN private/register level implementation.

Author

Millan Kumar (kumar.nosp@m.798@.nosp@m.purdu.nosp@m.e.ed.nosp@m.u)

Enumeration Type Documentation

PHAL_FDCAN_DefaultFilterAction_t

enum PHAL_FDCAN_DefaultFilterAction_t : uint32_t

Filter action values for RXGFC register Controls what happens to any frame that does not match any of the configured filters

Enumerator
FDCAN_PRIV_FILTER_ACCEPT_IN_RX_FIFO0
FDCAN_PRIV_FILTER_REJECT

Function Documentation

PHAL_FDCAN_priv_clearReceiveFifo0NewMessageInterruptFlag()

void PHAL_FDCAN_priv_clearReceiveFifo0NewMessageInterruptFlag

(

FDCAN_GlobalTypeDef *

fdcan

)

Clear the RX FIFO0 new message interrupt flag.

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PHAL_FDCAN_priv_clearTransmitCompleteInterruptFlag()

void PHAL_FDCAN_priv_clearTransmitCompleteInterruptFlag

(

FDCAN_GlobalTypeDef *

fdcan

)

Clear the TX complete interrupt flag.

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PHAL_FDCAN_priv_controlConfig()

void PHAL_FDCAN_priv_controlConfig

(

FDCAN_GlobalTypeDef *

fdcan

)

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PHAL_FDCAN_priv_enableClock()

void PHAL_FDCAN_priv_enableClock

(

void

)

Enable FDCAN kernel + peripheral clocks (PCLK1)

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PHAL_FDCAN_priv_enterConfig()

void PHAL_FDCAN_priv_enterConfig

(

FDCAN_GlobalTypeDef *

fdcan

)

Enter INIT mode and unlock configuration registers. Blocks until entered.

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PHAL_FDCAN_priv_exitConfig()

void PHAL_FDCAN_priv_exitConfig

(

FDCAN_GlobalTypeDef *

fdcan

)

Leave INIT mode, ending configuration. Blocks until left.

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PHAL_FDCAN_priv_getNBTP()

uint32_t PHAL_FDCAN_priv_getNBTP

(

PHAL_FDCAN_BaudRate_t

bit_rate

)

Compute the NBTP register value for one of the supported bit rates. 16-time-quantum nominal bit time (~87.5% sample point)

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PHAL_FDCAN_priv_ramBase()

uint32_t PHAL_FDCAN_priv_ramBase

(

const FDCAN_GlobalTypeDef *

fdcan

)

Base address of this peripheral's slice of shared message RAM.

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PHAL_FDCAN_priv_readReceiveFifo0NewMessageInterruptFlag()

bool PHAL_FDCAN_priv_readReceiveFifo0NewMessageInterruptFlag

(

const FDCAN_GlobalTypeDef *

fdcan

)

Check whether the RX FIFO0 new message interrupt flag is set.

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PHAL_FDCAN_priv_readRxElement()

bool PHAL_FDCAN_priv_readRxElement	(	FDCAN_GlobalTypeDef *	fdcan,
		CanMsgTypeDef_t *	msg )

Pop and decode the oldest element from RX FIFO0.

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PHAL_FDCAN_priv_readTransmitCompleteInterruptFlag()

bool PHAL_FDCAN_priv_readTransmitCompleteInterruptFlag

(

const FDCAN_GlobalTypeDef *

fdcan

)

Check whether the TX complete interrupt flag is set.

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PHAL_FDCAN_priv_readTxFifoQueueStatusFullFlag()

bool PHAL_FDCAN_priv_readTxFifoQueueStatusFullFlag

(

const FDCAN_GlobalTypeDef *

fdcan

)

Check whether the TX FIFO/Queue is full.

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PHAL_FDCAN_priv_setTransmitFifoQueueModeToFifo()

void PHAL_FDCAN_priv_setTransmitFifoQueueModeToFifo

(

FDCAN_GlobalTypeDef *

fdcan

)

Set TX FIFO/Queue mode to FIFO (not queue)

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PHAL_FDCAN_priv_writeExtendedFilters()

void PHAL_FDCAN_priv_writeExtendedFilters	(	FDCAN_GlobalTypeDef *	fdcan,
		const uint32_t *	xid_list,
		uint32_t	num_xid )

Set num_xid exact-match extended filters and forward to RX FIFO0.

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PHAL_FDCAN_priv_writeFilterAction()

void PHAL_FDCAN_priv_writeFilterAction	(	FDCAN_GlobalTypeDef *	fdcan,
		PHAL_FDCAN_DefaultFilterAction_t	action )

Write a filter action to RXGFC (accept/reject all)

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PHAL_FDCAN_priv_writeStandardFilters()

void PHAL_FDCAN_priv_writeStandardFilters	(	FDCAN_GlobalTypeDef *	fdcan,
		const uint32_t *	sid_list,
		uint32_t	num_sid )

Set num_sid exact-match standard filters and forward to RX FIFO0.

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PHAL_FDCAN_priv_writeTxElement()

void PHAL_FDCAN_priv_writeTxElement	(	FDCAN_GlobalTypeDef *	fdcan,
		CanMsgTypeDef_t *	msg )

Write one classic-CAN TX element for msg into the next free TX FIFO slot Not safe to call if the TX FIFO is full

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PHAL_FDCAN_setInterruptLines()

void PHAL_FDCAN_setInterruptLines

(

FDCAN_GlobalTypeDef *

fdcan

)

Set up RX new message -> line 0, TX complete -> line 1.

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Variable Documentation

FDCAN_PRIV_KER_CLK_HZ

uint32_t FDCAN_PRIV_KER_CLK_HZ = 16'000'000U

staticconstexpr

The FDCAN kernel clock frequency (the clock NBTP's prescaler divides down. Our HAL for FDCAN is always clocked from PCLK1. NOTE: delicate to PCLK1 changes!!

FDCAN_PRIV_RCC_FDCANCLKSOURCE_PCLK1

uint32_t FDCAN_PRIV_RCC_FDCANCLKSOURCE_PCLK1 = RCC_CCIPR_FDCANSEL_1

staticconstexpr

FDCAN clock is derived from PCLK1.

FDCAN_PRIV_SRAMCAN_FLE_NBR

uint32_t FDCAN_PRIV_SRAMCAN_FLE_NBR = 8

staticconstexpr

Max standard id filters.

FDCAN_PRIV_SRAMCAN_FLE_SIZE

uint32_t FDCAN_PRIV_SRAMCAN_FLE_SIZE = 2 * 4

staticconstexpr

FDCAN_PRIV_SRAMCAN_FLESA

uint32_t FDCAN_PRIV_SRAMCAN_FLESA = FDCAN_PRIV_SRAMCAN_FLSSA + FDCAN_PRIV_SRAMCAN_FLS_NBR * FDCAN_PRIV_SRAMCAN_FLS_SIZE

staticconstexpr

Filter List Extended Start Address

• the byte offset, within this instance's Message RAM slice, where the array of extended (29-bit ID) filter elements begins

FDCAN_PRIV_SRAMCAN_FLS_NBR

uint32_t FDCAN_PRIV_SRAMCAN_FLS_NBR = 28

staticconstexpr

FDCAN_PRIV_SRAMCAN_FLS_SIZE

uint32_t FDCAN_PRIV_SRAMCAN_FLS_SIZE = 1 * 4

staticconstexpr

TX FIFO Elements Number.

FDCAN_PRIV_SRAMCAN_FLSSA

uint32_t FDCAN_PRIV_SRAMCAN_FLSSA = 0

staticconstexpr

Filter List Standard Start Address

• the byte offset, within this instance's Message RAM slice, where the array of standard (11-bit ID) filter elements begins

FDCAN_PRIV_SRAMCAN_RF0_NBR

uint32_t FDCAN_PRIV_SRAMCAN_RF0_NBR = 3

staticconstexpr

Max extended id filters.

FDCAN_PRIV_SRAMCAN_RF0_SIZE

uint32_t FDCAN_PRIV_SRAMCAN_RF0_SIZE = 18 * 4

staticconstexpr

Size in bytes of one RX FIFO 0 element (set by the hardware format)

FDCAN_PRIV_SRAMCAN_RF0SA

uint32_t FDCAN_PRIV_SRAMCAN_RF0SA = FDCAN_PRIV_SRAMCAN_FLESA + FDCAN_PRIV_SRAMCAN_FLE_NBR * FDCAN_PRIV_SRAMCAN_FLE_SIZE

staticconstexpr

Rx FIFO 0 Start Address

• byte offset where the RX FIFO 0 element array begins in this instance's Message RAM slice

FDCAN_PRIV_SRAMCAN_RF1_NBR

uint32_t FDCAN_PRIV_SRAMCAN_RF1_NBR = 3

staticconstexpr

RX FIFO 0 Elements Number.

FDCAN_PRIV_SRAMCAN_RF1_SIZE

uint32_t FDCAN_PRIV_SRAMCAN_RF1_SIZE = 18 * 4

staticconstexpr

FDCAN_PRIV_SRAMCAN_RF1SA

uint32_t FDCAN_PRIV_SRAMCAN_RF1SA = FDCAN_PRIV_SRAMCAN_RF0SA + FDCAN_PRIV_SRAMCAN_RF0_NBR * FDCAN_PRIV_SRAMCAN_RF0_SIZE

staticconstexpr

FDCAN_PRIV_SRAMCAN_SIZE

uint32_t FDCAN_PRIV_SRAMCAN_SIZE = FDCAN_PRIV_SRAMCAN_TFQSA + FDCAN_PRIV_SRAMCAN_TFQ_NBR * FDCAN_PRIV_SRAMCAN_TFQ_SIZE

staticconstexpr

Bytes required/consumed by one instance's full Message RAM layout (filters + RX FIFOs + TX event FIFO + TX FIFO)

FDCAN_PRIV_SRAMCAN_TEF_NBR

uint32_t FDCAN_PRIV_SRAMCAN_TEF_NBR = 3

staticconstexpr

RX FIFO 1 Elements Number.

FDCAN_PRIV_SRAMCAN_TEF_SIZE

uint32_t FDCAN_PRIV_SRAMCAN_TEF_SIZE = 2 * 4

staticconstexpr

FDCAN_PRIV_SRAMCAN_TEFSA

uint32_t FDCAN_PRIV_SRAMCAN_TEFSA = FDCAN_PRIV_SRAMCAN_RF1SA + FDCAN_PRIV_SRAMCAN_RF1_NBR * FDCAN_PRIV_SRAMCAN_RF1_SIZE

staticconstexpr

FDCAN_PRIV_SRAMCAN_TFQ_NBR

uint32_t FDCAN_PRIV_SRAMCAN_TFQ_NBR = 3

staticconstexpr

TX Event FIFO Elements Number.

FDCAN_PRIV_SRAMCAN_TFQ_SIZE

uint32_t FDCAN_PRIV_SRAMCAN_TFQ_SIZE = 18 * 4

staticconstexpr

Size in bytes of one TX FIFO/queue element (set by the hardware format)

FDCAN_PRIV_SRAMCAN_TFQSA

uint32_t FDCAN_PRIV_SRAMCAN_TFQSA = FDCAN_PRIV_SRAMCAN_TEFSA + FDCAN_PRIV_SRAMCAN_TEF_NBR * FDCAN_PRIV_SRAMCAN_TEF_SIZE

staticconstexpr

Tx FIFO/Queue Start Address

• byte offset where the TX FIFO/queue element array begins in this instance's Message RAM slice