g474ret6.h

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#ifndef PHAL_G4_PIN_DEFS_G474RET6_H
#define PHAL_G4_PIN_DEFS_G474RET6_H
 
#include "stm32g474xx.h"
 
#include "common/phal_G4/gpio/gpio.h"
 
 
// FDCAN ---------------------------------------------------------------------//
// FDCAN1
static constexpr uint8_t PHAL_PIN_DEFS_AF_NUM_FDCAN1 = 9;
// PA11 = FDCAN1 RX, PA12 = FDCAN1 TX
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_FDCAN1_RX_PA11 = PHAL_GPIO_INIT_AF(GPIOA, 11, PHAL_PIN_DEFS_AF_NUM_FDCAN1, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_OPEN_DRAIN, GPIO_INPUT_OPEN_DRAIN);
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_FDCAN1_TX_PA12 = PHAL_GPIO_INIT_AF(GPIOA, 12, PHAL_PIN_DEFS_AF_NUM_FDCAN1, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_OPEN_DRAIN);
// PB8 = FDCAN1 RX, PB9 = FDCAN1 TX
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_FDCAN1_RX_PB8 = PHAL_GPIO_INIT_AF(GPIOB, 8, PHAL_PIN_DEFS_AF_NUM_FDCAN1, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_OPEN_DRAIN, GPIO_INPUT_OPEN_DRAIN);
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_FDCAN1_TX_PB9 = PHAL_GPIO_INIT_AF(GPIOB, 9, PHAL_PIN_DEFS_AF_NUM_FDCAN1, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_OPEN_DRAIN);
 
// FDCAN2
static constexpr uint8_t PHAL_PIN_DEFS_AF_NUM_FDCAN2 = 9;
// PB12 = FDCAN2 RX, PB13 = FDCAN2 TX
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_FDCAN2_RX_PB12 = PHAL_GPIO_INIT_AF(GPIOB, 12, PHAL_PIN_DEFS_AF_NUM_FDCAN2, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_OPEN_DRAIN, GPIO_INPUT_OPEN_DRAIN);
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_FDCAN2_TX_PB13 = PHAL_GPIO_INIT_AF(GPIOB, 13, PHAL_PIN_DEFS_AF_NUM_FDCAN2, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_OPEN_DRAIN);
// PB5 = FDCAN2 RX, PB6 = FDCAN2 TX
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_FDCAN2_RX_PB5 = PHAL_GPIO_INIT_AF(GPIOB, 5, PHAL_PIN_DEFS_AF_NUM_FDCAN2, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_OPEN_DRAIN, GPIO_INPUT_OPEN_DRAIN);
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_FDCAN2_TX_PB6 = PHAL_GPIO_INIT_AF(GPIOB, 6, PHAL_PIN_DEFS_AF_NUM_FDCAN2, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_OPEN_DRAIN);
 
// FDCAN3
static constexpr uint8_t PHAL_PIN_DEFS_AF_NUM_FDCAN3 = 11;
// PA8 = FDCAN3 RX, PB4 = FDCAN3 TX
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_FDCAN3_RX_PA8 = PHAL_GPIO_INIT_AF(GPIOA, 8, PHAL_PIN_DEFS_AF_NUM_FDCAN3, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_OPEN_DRAIN, GPIO_INPUT_OPEN_DRAIN);
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_FDCAN3_TX_PB4 = PHAL_GPIO_INIT_AF(GPIOB, 4, PHAL_PIN_DEFS_AF_NUM_FDCAN3, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_OPEN_DRAIN);
// PA15 = FDCAN3 RX, PB3 = FDCAN3 TX
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_FDCAN3_RX_PA15 = PHAL_GPIO_INIT_AF(GPIOA, 15, PHAL_PIN_DEFS_AF_NUM_FDCAN3, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_OPEN_DRAIN, GPIO_INPUT_OPEN_DRAIN);
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_FDCAN3_TX_PB3  = PHAL_GPIO_INIT_AF(GPIOB, 3,  PHAL_PIN_DEFS_AF_NUM_FDCAN3, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_OPEN_DRAIN);
//----------------------------------------------------------------------------//
 
// USART ---------------------------------------------------------------------//
// USART1
static constexpr uint8_t PHAL_PIN_DEFS_AF_NUM_USART1 = 7;
// PA9 = USART1 TX, PA10 = USART1 RX
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_USART1_TX_PA9  = PHAL_GPIO_INIT_AF(GPIOA, 9,  PHAL_PIN_DEFS_AF_NUM_USART1, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_OPEN_DRAIN);
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_USART1_RX_PA10 = PHAL_GPIO_INIT_AF(GPIOA, 10, PHAL_PIN_DEFS_AF_NUM_USART1, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_OPEN_DRAIN, GPIO_INPUT_OPEN_DRAIN);
 
// USART2
static constexpr uint8_t PHAL_PIN_DEFS_AF_NUM_USART2 = 7;
// PA2 = USART2 TX, PA3 = USART2 RX
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_USART2_TX_PA2 = PHAL_GPIO_INIT_AF(GPIOA, 2, PHAL_PIN_DEFS_AF_NUM_USART2, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_OPEN_DRAIN);
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_USART2_RX_PA3 = PHAL_GPIO_INIT_AF(GPIOA, 3, PHAL_PIN_DEFS_AF_NUM_USART2, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_OPEN_DRAIN, GPIO_INPUT_OPEN_DRAIN);
// PD5 = USART2 TX, PD6 = USART2 RX
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_USART2_TX_PD5 = PHAL_GPIO_INIT_AF(GPIOD, 5, PHAL_PIN_DEFS_AF_NUM_USART2, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_OPEN_DRAIN);
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_USART2_RX_PD6 = PHAL_GPIO_INIT_AF(GPIOD, 6, PHAL_PIN_DEFS_AF_NUM_USART2, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_OPEN_DRAIN, GPIO_INPUT_OPEN_DRAIN);
 
// USART3
static constexpr uint8_t PHAL_PIN_DEFS_AF_NUM_USART3 = 7;
// PC10 = USART3 TX, PC11 = USART3 RX
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_USART3_TX_PC10 = PHAL_GPIO_INIT_AF(GPIOC, 10, PHAL_PIN_DEFS_AF_NUM_USART3, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_OPEN_DRAIN);
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_USART3_RX_PC11 = PHAL_GPIO_INIT_AF(GPIOC, 11, PHAL_PIN_DEFS_AF_NUM_USART3, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_OPEN_DRAIN, GPIO_INPUT_OPEN_DRAIN);
// PB10 = USART3 TX, PB11 = USART3 RX
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_USART3_TX_PB10 = PHAL_GPIO_INIT_AF(GPIOB, 10, PHAL_PIN_DEFS_AF_NUM_USART3, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_OPEN_DRAIN);
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_USART3_RX_PB11 = PHAL_GPIO_INIT_AF(GPIOB, 11, PHAL_PIN_DEFS_AF_NUM_USART3, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_OPEN_DRAIN, GPIO_INPUT_OPEN_DRAIN);
//----------------------------------------------------------------------------//
 
 
// SPI -----------------------------------------------------------------------//
// SPI1
static constexpr uint8_t PHAL_PIN_DEFS_AF_NUM_SPI1 = 5;
// PA5 = SPI1 SCK, PA6 = SPI1 MISO, PA7 = SPI1 MOSI, PA4 or PA15 = SPI1 NSS
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_SPI1_SCK_PA5  = PHAL_GPIO_INIT_AF(GPIOA, 5,  PHAL_PIN_DEFS_AF_NUM_SPI1, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_OPEN_DRAIN);
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_SPI1_MISO_PA6 = PHAL_GPIO_INIT_AF(GPIOA, 6,  PHAL_PIN_DEFS_AF_NUM_SPI1, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_PULL_UP);
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_SPI1_MOSI_PA7 = PHAL_GPIO_INIT_AF(GPIOA, 7,  PHAL_PIN_DEFS_AF_NUM_SPI1, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_OPEN_DRAIN);
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_SPI1_NSS_PA4  = PHAL_GPIO_INIT_AF(GPIOA, 4,  PHAL_PIN_DEFS_AF_NUM_SPI1, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_OPEN_DRAIN);
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_SPI1_NSS_PA15 = PHAL_GPIO_INIT_AF(GPIOA, 15, PHAL_PIN_DEFS_AF_NUM_SPI1, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_OPEN_DRAIN);
 
// SPI2
static constexpr uint8_t PHAL_PIN_DEFS_AF_NUM_SPI2 = 5;
// PB13 = SPI2 SCK, PB14 = SPI2 MISO, PB15 = SPI2 MOSI, PB12 = SPI2 NSS
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_SPI2_SCK_PB13  = PHAL_GPIO_INIT_AF(GPIOB, 13, PHAL_PIN_DEFS_AF_NUM_SPI2, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_OPEN_DRAIN);
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_SPI2_MISO_PB14 = PHAL_GPIO_INIT_AF(GPIOB, 14, PHAL_PIN_DEFS_AF_NUM_SPI2, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_PULL_UP);
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_SPI2_MOSI_PB15 = PHAL_GPIO_INIT_AF(GPIOB, 15, PHAL_PIN_DEFS_AF_NUM_SPI2, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_OPEN_DRAIN);
static const PHAL_GPIO_InitConfig_t PHAL_PIN_DEFS_SPI2_NSS_PB12  = PHAL_GPIO_INIT_AF(GPIOB, 12, PHAL_PIN_DEFS_AF_NUM_SPI2, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_OPEN_DRAIN);
//----------------------------------------------------------------------------//
 
 
#endif // PHAL_G4_PIN_DEFS_G474RET6_H