gpio_priv.h File Reference

G4 GPIO private/register level implementation. More...

#include "common/phal_G4/gpio/gpio.h"

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Functions
bool	PHAL_GPIO_priv_enableClock (GPIO_TypeDef *bank)
	Enable the AHB2 clock for bank's port (GPIOA-GPIOG).
void	PHAL_GPIO_priv_setMode (GPIO_TypeDef *bank, uint8_t pin, PHAL_GPIO_PinType_t type)
	Set MODER's field for pin to type. Caller must have validated pin <= 15.
void	PHAL_GPIO_priv_setOutputSpeed (GPIO_TypeDef *bank, uint8_t pin, PHAL_GPIO_OutputSpeed_t speed)
	Set OSPEEDR's field for pin. Caller must have validated pin <= 15.
void	PHAL_GPIO_priv_setOutputType (GPIO_TypeDef *bank, uint8_t pin, PHAL_GPIO_OutputPull_t otype)
	Set OTYPER's field for pin. Caller must have validated pin <= 15.
void	PHAL_GPIO_priv_setPull (GPIO_TypeDef *bank, uint8_t pin, PHAL_GPIO_InputPull_t pull)
	Set PUPDR's field for pin. Caller must have validated pin <= 15.
void	PHAL_GPIO_priv_setAltFunction (GPIO_TypeDef *bank, uint8_t pin, uint8_t af_num)
	Set AFR's field for pin. Caller must have validated pin <= 15.
bool	PHAL_GPIO_priv_read (const GPIO_TypeDef *bank, uint8_t pin)
	Read IDR's bit for pin. Caller must have validated pin <= 15.
void	PHAL_GPIO_priv_write (GPIO_TypeDef *bank, uint8_t pin, bool value)
	Write BSRR to atomically set/reset pin. Caller must have validated pin <= 15.
void	PHAL_GPIO_priv_toggle (GPIO_TypeDef *bank, uint8_t pin)
	Read then invert pin via BSRR. Caller must have validated pin <= 15.

Variables
static constexpr uint32_t	GPIO_PRIV_MODER_FIELD_BITS = 2U
static constexpr uint32_t	GPIO_PRIV_OSPEEDR_FIELD_BITS = 2U
static constexpr uint32_t	GPIO_PRIV_OTYPER_FIELD_BITS = 1U
static constexpr uint32_t	GPIO_PRIV_PUPDR_FIELD_BITS = 2U
static constexpr uint32_t	GPIO_PRIV_AFR_FIELD_BITS = 4U
static constexpr uint32_t	GPIO_PRIV_PORT_STRIDE = 0x400U
static constexpr uint32_t	GPIO_PRIV_RCC_ENABLE_BITS []
static constexpr uint32_t	GPIO_PRIV_NUM_PORTS = sizeof(GPIO_PRIV_RCC_ENABLE_BITS) / sizeof(GPIO_PRIV_RCC_ENABLE_BITS[0])

Detailed Description

G4 GPIO private/register level implementation.

Author

Millan Kumar (kumar.nosp@m.798@.nosp@m.purdu.nosp@m.e.ed.nosp@m.u)

Function Documentation

PHAL_GPIO_priv_enableClock()

bool PHAL_GPIO_priv_enableClock

(

GPIO_TypeDef *

bank

)

Enable the AHB2 clock for bank's port (GPIOA-GPIOG).

Returns

true on success; false if bank is not a recognized GPIO port

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PHAL_GPIO_priv_read()

bool PHAL_GPIO_priv_read	(	const GPIO_TypeDef *	bank,
		uint8_t	pin )

Read IDR's bit for pin. Caller must have validated pin <= 15.

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PHAL_GPIO_priv_setAltFunction()

void PHAL_GPIO_priv_setAltFunction	(	GPIO_TypeDef *	bank,
		uint8_t	pin,
		uint8_t	af_num )

Set AFR's field for pin. Caller must have validated pin <= 15.

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PHAL_GPIO_priv_setMode()

void PHAL_GPIO_priv_setMode	(	GPIO_TypeDef *	bank,
		uint8_t	pin,
		PHAL_GPIO_PinType_t	type )

Set MODER's field for pin to type. Caller must have validated pin <= 15.

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PHAL_GPIO_priv_setOutputSpeed()

void PHAL_GPIO_priv_setOutputSpeed	(	GPIO_TypeDef *	bank,
		uint8_t	pin,
		PHAL_GPIO_OutputSpeed_t	speed )

Set OSPEEDR's field for pin. Caller must have validated pin <= 15.

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PHAL_GPIO_priv_setOutputType()

void PHAL_GPIO_priv_setOutputType	(	GPIO_TypeDef *	bank,
		uint8_t	pin,
		PHAL_GPIO_OutputPull_t	otype )

Set OTYPER's field for pin. Caller must have validated pin <= 15.

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PHAL_GPIO_priv_setPull()

void PHAL_GPIO_priv_setPull	(	GPIO_TypeDef *	bank,
		uint8_t	pin,
		PHAL_GPIO_InputPull_t	pull )

Set PUPDR's field for pin. Caller must have validated pin <= 15.

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PHAL_GPIO_priv_toggle()

void PHAL_GPIO_priv_toggle	(	GPIO_TypeDef *	bank,
		uint8_t	pin )

Read then invert pin via BSRR. Caller must have validated pin <= 15.

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PHAL_GPIO_priv_write()

void PHAL_GPIO_priv_write	(	GPIO_TypeDef *	bank,
		uint8_t	pin,
		bool	value )

Write BSRR to atomically set/reset pin. Caller must have validated pin <= 15.

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Variable Documentation

GPIO_PRIV_AFR_FIELD_BITS

uint32_t GPIO_PRIV_AFR_FIELD_BITS = 4U

staticconstexpr

GPIO_PRIV_MODER_FIELD_BITS

uint32_t GPIO_PRIV_MODER_FIELD_BITS = 2U

staticconstexpr

GPIO_PRIV_NUM_PORTS

uint32_t GPIO_PRIV_NUM_PORTS = sizeof(GPIO_PRIV_RCC_ENABLE_BITS) / sizeof(GPIO_PRIV_RCC_ENABLE_BITS[0])

staticconstexpr

GPIO_PRIV_OSPEEDR_FIELD_BITS

uint32_t GPIO_PRIV_OSPEEDR_FIELD_BITS = 2U

staticconstexpr

GPIO_PRIV_OTYPER_FIELD_BITS

uint32_t GPIO_PRIV_OTYPER_FIELD_BITS = 1U

staticconstexpr

GPIO_PRIV_PORT_STRIDE

uint32_t GPIO_PRIV_PORT_STRIDE = 0x400U

staticconstexpr

GPIO_PRIV_PUPDR_FIELD_BITS

uint32_t GPIO_PRIV_PUPDR_FIELD_BITS = 2U

staticconstexpr

GPIO_PRIV_RCC_ENABLE_BITS

uint32_t GPIO_PRIV_RCC_ENABLE_BITS[]

staticconstexpr

Initial value:

= {
    RCC_AHB2ENR_GPIOAEN,
    RCC_AHB2ENR_GPIOBEN,
    RCC_AHB2ENR_GPIOCEN,
    RCC_AHB2ENR_GPIODEN,
    RCC_AHB2ENR_GPIOEEN,
    RCC_AHB2ENR_GPIOFEN,
    RCC_AHB2ENR_GPIOGEN,
}