rcc.c File Reference

#include "common/phal_F4/rcc/rcc.h"

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Functions
uint8_t	PHAL_configureClockRates (ClockRateConfig_t *config)
	Configure all AHB/APB/System clocks from the provided configuration.
bool	PHAL_configurePLLVCO (PLLSrc_t pll_source, uint32_t vco_output_rate_target_hz)
	Configure PLL VCO Clock rate The VCO clock is the input clock for the different PLL outputs. Each PLL output will divide the VCO clock to get its output.
bool	PHAL_configurePLLSystemClock (uint32_t system_clock_target_hz)
	Configure PLL CLK as the System Clock at the desired target frequency. SHOULD BE DONE BEFORE ANY OF THE AHB OR APB CLOCKS ARE CHANGED.
bool	PHAL_configureHSISystemClock ()
	Configure HSI CLK as the System Clock. SHOULD BE DONE BEFORE ANY OF THE AHB OR APB CLOCKS ARE CHANGED.
bool	PHAL_configureHSESystemClock ()
	Configure HSE CLK as the System Clock. SHOULD BE DONE BEFORE ANY OF THE AHB OR APB CLOCKS ARE CHANGED.
bool	PHAL_configureAHBClock (uint32_t ahb_clock_target_hz)
	Configure AHB Clock rate by modifying the AHB prescaler value.
bool	PHAL_configureAPB1Clock (uint32_t apb1_clock_target_hz)
	Configure APB1 Clock rate by modifying the APB1 prescaler value.
bool	PHAL_configureAPB2Clock (uint32_t apb2_clock_target_hz)
	Configure APB1 Clock rate by modifying the APB2 prescaler value.
void	PHAL_trimHSI (uint8_t trim_val)
	Trim the HSI clock 0 <= trim_val <= 31 17 = increase speed by ~0.2% 15 = decrease speed by ~0.2%.
bool	PHAL_enableMCO1 (GPIO_TypeDef *bank, uint8_t pin, MCO1Source_t source, MCODivisor_t division)
	Enable the Clock Out Pin 1 It is highly recommended to change this only after reset before enabling the external oscillators and the PLL.

Variables
uint32_t	APB1ClockRateHz
uint32_t	APB2ClockRateHz
uint32_t	AHBClockRateHz
uint32_t	PLLClockRateHz

Function Documentation

PHAL_configureAHBClock()

bool PHAL_configureAHBClock

(

uint32_t

ahb_clock_target_hz

)

Configure AHB Clock rate by modifying the AHB prescaler value.

Parameters

ahb_clock_target_hz

Returns

true Successfully configured AHB clock rate to

Parameters

ahb_clock_target_hz

Returns

false

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PHAL_configureAPB1Clock()

bool PHAL_configureAPB1Clock

(

uint32_t

apb1_clock_target_hz

)

Configure APB1 Clock rate by modifying the APB1 prescaler value.

Parameters

apb1_clock_target_hz

Returns

true Successfully configured AHB clock rate to

Parameters

apb1_clock_target_hz

Returns

false

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PHAL_configureAPB2Clock()

bool PHAL_configureAPB2Clock

(

uint32_t

apb2_clock_target_hz

)

Configure APB1 Clock rate by modifying the APB2 prescaler value.

Parameters

apb2_clock_target_hz

Returns

true Successfully configured AHB clock rate to

Parameters

apb2_clock_target_hz

Returns

false

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PHAL_configureClockRates()

uint8_t PHAL_configureClockRates

(

ClockRateConfig_t *

config

)

Configure all AHB/APB/System clocks from the provided configuration.

Parameters

config

Configuration to try to match

Returns

Binary encoded representation of which clocks were unsuccessfuly configured. return value of 0 means all clocks were sucessfully configured.

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PHAL_configureHSESystemClock()

bool PHAL_configureHSESystemClock

(

)

Configure HSE CLK as the System Clock. SHOULD BE DONE BEFORE ANY OF THE AHB OR APB CLOCKS ARE CHANGED.

Returns

true Successfully configured HSE clock as system clock

false

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PHAL_configureHSISystemClock()

bool PHAL_configureHSISystemClock

(

)

Configure HSI CLK as the System Clock. SHOULD BE DONE BEFORE ANY OF THE AHB OR APB CLOCKS ARE CHANGED.

Returns

true Successfully configured HSI clock as system clock

false

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PHAL_configurePLLSystemClock()

bool PHAL_configurePLLSystemClock

(

uint32_t

system_clock_target_hz

)

Configure PLL CLK as the System Clock at the desired target frequency. SHOULD BE DONE BEFORE ANY OF THE AHB OR APB CLOCKS ARE CHANGED.

Parameters

system_clock_target_hz

Returns

true Successfully configured PLL clock as system clock

false

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PHAL_configurePLLVCO()

bool PHAL_configurePLLVCO	(	PLLSrc_t	pll_source,
		uint32_t	vco_output_rate_target_hz )

Configure PLL VCO Clock rate The VCO clock is the input clock for the different PLL outputs. Each PLL output will divide the VCO clock to get its output.

Parameters

PLL	Input rate for PLL, determined by PLL source
vco_output_rate_target_hz	Target rate for PLL output

Returns

true

false

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PHAL_enableMCO1()

bool PHAL_enableMCO1	(	GPIO_TypeDef *	bank,
		uint8_t	pin,
		MCO1Source_t	source,
		MCODivisor_t	division )

Enable the Clock Out Pin 1 It is highly recommended to change this only after reset before enabling the external oscillators and the PLL.

This function should be called after GPIO initialization using GPIO_INIT_MCO1_PA8

Parameters

bank	GPIO bank
pin	GPIO bank
source	Clock source to send to the pin
division	Division of clock source sent to the pin

Returns

true Successfully enabled the clock out

false

PHAL_trimHSI()

void PHAL_trimHSI

(

uint8_t

trim_val

)

Trim the HSI clock 0 <= trim_val <= 31 17 = increase speed by ~0.2% 15 = decrease speed by ~0.2%.

Variable Documentation

AHBClockRateHz

uint32_t AHBClockRateHz

APB1ClockRateHz

uint32_t APB1ClockRateHz

APB2ClockRateHz

uint32_t APB2ClockRateHz

PLLClockRateHz

uint32_t PLLClockRateHz