spi.h

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#ifndef _PHAL_SPI_H
#define _PHAL_SPI_H
 
#include <stddef.h>
 
#include "common/phal_F4/dma/dma.h"
#include "common/phal_F4/gpio/gpio.h"
#include "common/phal_F4/phal_F4.h"
#include "common/phal_F4/rcc/rcc.h"
 
typedef struct
{
    uint32_t data_rate; 
    uint8_t data_len; 
    bool nss_sw; 
    GPIO_TypeDef* nss_gpio_port; 
    uint32_t nss_gpio_pin; 
 
    dma_init_t* rx_dma_cfg; 
    dma_init_t* tx_dma_cfg; 
 
    volatile bool _busy; 
    volatile bool _error; 
    volatile bool _direct_mode_error; 
    volatile bool _fifo_overrun; 
 
    SPI_TypeDef* periph; 
} SPI_InitConfig_t;
 
bool PHAL_SPI_init(SPI_InitConfig_t* handle);
 
bool PHAL_SPI_transfer(SPI_InitConfig_t* spi, const uint8_t* out_data, const uint32_t data_len, const uint8_t* in_data);
 
bool PHAL_SPI_transfer_noDMA(SPI_InitConfig_t* spi, const uint8_t* out_data, uint32_t txlen, uint32_t rxlen, uint8_t* in_data);
 
bool PHAL_SPI_busy(SPI_InitConfig_t* cfg);
 
uint8_t PHAL_SPI_writeByte(SPI_InitConfig_t* spi, uint8_t address, uint8_t writeDat);
 
uint8_t PHAL_SPI_readByte(SPI_InitConfig_t* spi, uint8_t address, bool skipDummy);
 
void PHAL_SPI_ForceReset(SPI_InitConfig_t* spi);
 
// SPI Configuration macros
#define SPI1_RXDMA_CONT_CONFIG(rx_addr_, priority_) \
    { \
        .periph_addr      = (uint32_t)&(SPI1->DR), \
        .mem_addr         = (uint32_t)(rx_addr_), \
        .tx_size          = 1, \
        .increment        = false, \
        .circular         = false, \
        .dir              = 0b0, \
        .mem_inc          = true, \
        .periph_inc       = false, \
        .mem_to_mem       = false, \
        .priority         = (priority_), \
        .mem_size         = 0b00, \
        .periph_size      = 0b00, \
        .tx_isr_en        = false, \
        .dma_chan_request = 0b0011, \
        .stream_idx       = 2, \
        .periph           = DMA2, \
        .stream           = DMA2_Stream2}
 
#define SPI1_TXDMA_CONT_CONFIG(tx_addr_, priority_) \
    { \
        .periph_addr      = (uint32_t)&(SPI1->DR), \
        .mem_addr         = (uint32_t)(tx_addr_), \
        .tx_size          = 1, \
        .increment        = false, \
        .circular         = false, \
        .dir              = 0b1, \
        .mem_inc          = true, \
        .periph_inc       = false, \
        .mem_to_mem       = false, \
        .priority         = (priority_), \
        .mem_size         = 0b00, \
        .periph_size      = 0b00, \
        .tx_isr_en        = true, \
        .dma_chan_request = 0b0011, \
        .stream_idx       = 3, \
        .periph           = DMA2, \
        .stream           = DMA2_Stream3}
 
#define SPI2_TXDMA_CONT_CONFIG(tx_addr_, priority_) \
    { \
        .periph_addr      = (uint32_t)&(SPI2->DR), \
        .mem_addr         = (uint32_t)(tx_addr_), \
        .tx_size          = 1, \
        .increment        = false, \
        .circular         = false, \
        .dir              = 0b1, \
        .mem_inc          = true, \
        .periph_inc       = false, \
        .mem_to_mem       = false, \
        .priority         = (priority_), \
        .mem_size         = 0b00, \
        .periph_size      = 0b00, \
        .tx_isr_en        = true, \
        .dma_chan_request = 0b0000, \
        .stream_idx       = 4, \
        .periph           = DMA1, \
        .stream           = DMA1_Stream4}
 
#define SPI2_RXDMA_CONT_CONFIG(rx_addr_, priority_) \
    { \
        .periph_addr      = (uint32_t)&(SPI2->DR), \
        .mem_addr         = (uint32_t)(rx_addr_), \
        .tx_size          = 1, \
        .increment        = false, \
        .circular         = false, \
        .dir              = 0b0, \
        .mem_inc          = true, \
        .periph_inc       = false, \
        .mem_to_mem       = false, \
        .priority         = (priority_), \
        .mem_size         = 0b00, \
        .periph_size      = 0b00, \
        .tx_isr_en        = false, \
        .dma_chan_request = 0b0000, \
        .stream_idx       = 3, \
        .periph           = DMA1, \
        .stream           = DMA1_Stream3}
 
#endif /* _PHAL_SPI_H */