rcc.h File Reference

G4 RCC public API implementation. More...

#include <stdbool.h>
#include <stdint.h>
#include "stm32g474xx.h"

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Enumerations
enum	PHAL_RCC_Mode_t { PHAL_RCC_HSI_16MHZ , PHAL_RCC_HSI_170MHZ , PHAL_RCC_HSE_16MHZ , PHAL_RCC_HSE_170MHZ }
	Supported system clock configurations. More...

Functions
void	PHAL_RCC_init (PHAL_RCC_Mode_t mode)
	Configure the system, AHB, APB1, and APB2 clocks for a supported clock tree.
uint32_t	PHAL_RCC_getSystemClockHz (void)
uint32_t	PHAL_RCC_getAHBClockHz (void)
uint32_t	PHAL_RCC_getAPB1ClockHz (void)
uint32_t	PHAL_RCC_getAPB2ClockHz (void)

Detailed Description

G4 RCC public API implementation.

Author

Millan Kumar (kumar.nosp@m.798@.nosp@m.purdu.nosp@m.e.ed.nosp@m.u)

Enumeration Type Documentation

PHAL_RCC_Mode_t

enum PHAL_RCC_Mode_t

Supported system clock configurations.

Every mode configures AHB, APB1, and APB2 to run undivided at the resulting system clock rate

Enumerator
PHAL_RCC_HSI_16MHZ	HSI16 direct, no PLL, 16 MHz system clock
PHAL_RCC_HSI_170MHZ	HSI16 through the PLL, 170 MHz (boost mode)
PHAL_RCC_HSE_16MHZ	HSE direct, no PLL, 16 MHz system clock
PHAL_RCC_HSE_170MHZ	HSE through the PLL, 170 MHz (boost mode)

Function Documentation

PHAL_RCC_getAHBClockHz()

uint32_t PHAL_RCC_getAHBClockHz

(

void

)

Returns

the current AHB (HCLK) rate in Hz

PHAL_RCC_getAPB1ClockHz()

uint32_t PHAL_RCC_getAPB1ClockHz

(

void

)

Returns

the current APB1 (PCLK1) rate in Hz

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PHAL_RCC_getAPB2ClockHz()

uint32_t PHAL_RCC_getAPB2ClockHz

(

void

)

Returns

the current APB2 (PCLK2) rate in Hz

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PHAL_RCC_getSystemClockHz()

uint32_t PHAL_RCC_getSystemClockHz

(

void

)

Returns

the current system clock (SYSCLK) rate in Hz

PHAL_RCC_init()

void PHAL_RCC_init

(

PHAL_RCC_Mode_t

mode

)

Configure the system, AHB, APB1, and APB2 clocks for a supported clock tree.

• The *_16MHZ modes run directly from the input oscillator (HSI16, or the board's 16 MHz HSE input in bypass mode) with no PLL
  • 0 Flash wait states
  • AHB = APB1 = APB2 = 16 MHz
• The *_170MHZ modes feed the input oscillator through the PLL (PLLM=4, PLLN=85, PLLR=2) for a clock speed of exactly 170 MHz
  • Enable Range 1 boost mode
  • Set 4 Flash wait states
  • AHB = APB1 = APB2 = 170 MHz

The unselected input oscillator will be disabled once this function ends:

• HSI is on by default out of reset
• If HSI is selected, we don't turn it off
• For an HSE mode, HSI is switched off once it's no longer needed

Parameters

mode	one of the four supported clock configurations

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